TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is used on
Numonyx™ Embedded Flash Memory (J3 v. D), a Clear Status Register command must
be executed after issuing the Set Enhanced Configuration Register command. See
Table 17
for further details.
Table 16: Enhanced Configuration Register
Page
Reserved
Length
ECR
ECR
ECR
ECR
ECR
15
14
13
12
11
BITS
ECR[15:14]
RFU
• “1” = 8 Word Page mode
ECR[13]
• “0” = 4 Word Page mode
ECR[12:0]
RFU
Table 17: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Bus
Command
Cycles
Required
Set Enhanced Configuration
2
Register (Set ECR)
1. X = Any valid address within the device. ECD = Enhanced Configuration Register Data
8.1.2
Output Disable
With CEx asserted, and OE# at a logic-high level (V
Output signals D[15:0] are placed in a high-impedance state.
8.2
Bus Writes
Writing or Programming to the device, is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
• Reading of array data
• Common Flash Interface (CFI) data
• Identifier codes, inspection, and clearing of the Status Register
• Block Erasure, Program, and Lock-bit Configuration (when V
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
November 2007
308551-05
Reserved
ECR
ECR
ECR
ECR
ECR
10
9
8
7
6
DESCRIPTION
First Bus Cycle
(1)
Oper
Addr
Data
Write
ECD
0060h
ECR
ECR
ECR
ECR
ECR
5
4
3
2
1
NOTES
All bits should be set to 0.
All bits should be set to 0.
Second Bus Cycle
(1)
Oper
Addr
Data
Write
ECD
0004h
), the device outputs are disabled.
IH
= V
)
PEN
PENH
Datasheet
ECR
0
33