TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables
the device (see
Table 15 on page
8.3
Standby
CE0, CE1, and CE2 can disable the device (see
standby mode. This manipulation of CEx substantially reduces device power
consumption. D[15:0] outputs are placed in a high-impedance state independent of
OE#. If deselected during block erase, program, or lock-bit configuration, the WSM
continues functioning, and consuming active power until the operation completes.
8.3.1
Reset/Power-Down
RP# at V
initiates the reset/power-down mode.
IL
In read modes, RP#-low deselects the memory, places output drivers in a high-
impedance state, and turns off numerous internal circuits. RP# must be held low for a
minimum of t
PLPH
memory access outputs are valid. After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and Status Register is set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and remains low for a maximum time
of t
+ t
PLPH
PHRH
are no longer valid; the data may be partially corrupted after a program or partially
altered after an erase or lock-bit configuration. Time t
logic-high (V
) before another command can be written.
IH
As with any automated device, it is important to assert RP# during system reset. When
the system comes out of reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed during Block Erase, Program,
or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx Flash memories allow proper initialization
following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
8.4
Device Commands
When the V
voltage ≤ V
PEN
identifier codes, or blocks are enabled. Placing V
erase, program, and lock-bit configuration operations. Device operations are selected
by writing specific commands to the Command User Interface (CUI). The CUI does not
occupy an addressable memory location. It is the mechanism through which the flash
device is controlled.
A command sequence is issued in two consecutive write cycles - a Setup command
followed by a Confirm command. However, some commands are single-cycle
commands consisting of a setup command only. Generally, commands that alter the
contents of the flash device, such as Program or Erase, require at least two write cycles
to guard against inadvertent changes to the flash device. Flash commands fall into two
categories: Basic Commands and Extended Commands. Basic commands are
recognized by all Numonyx Flash devices, and are used to perform common flash
operations such as selecting the read mode, programming the array, or erasing blocks.
Extended commands are product-dependant; they are used to perform additional
features such as software block locking.
Numonyx™ Embedded Flash Memory (J3 v. D).
Datasheet
34
31). Standard microprocessor write timings are used.
. Time t
is required after return from reset mode until initial
PHQV
until the reset operation is complete. Memory contents being altered
, only read operations from the Status Register, CFI,
PENLK
Table 18
Numonyx™ Embedded Flash Memory (J3 v. D)
Table 15 on page
31) and place it in
is required after RP# goes to
PHWL
on V
additionally enables block
PENH
PEN
describes all applicable commands on
November 2007
308551-05