TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 

Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
9.1.1
Clearing the Status Register
The Status Register (SR) contain status and error bits which are set by the device. SR
status bits are cleared by the device, however SR error bits are cleared by issuing the
Clear Status Register command. Resetting the device also clears the Status Register.
Table 20: Clear Status Register Command Bus-Cycle
Command
Clear Status Register
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address.
Issuing the Clear Status Register command places the device in Read Status Register
mode.
Note:
Care should be taken to avoid Status Register ambiguity. If a command sequence error
occurs while in an Erase Suspend condition, the Status Register will indicate a
Command Sequence error by setting SR4 and SR5. When the erase operation is
resumed (and finishes), any errors that may have occurred during the erase operation
will be masked by the Command Sequence error. To avoid this situation, clear the
Status Register prior to resuming a suspended erase operation. The Clear Status
Register command functions independent of the voltage level on VPEN.
9.2
Read Operations
Four types of data can be read from the device: array data, device information, CFI
data, and device status. Upon power-up or return from reset, the device defaults to Read Array mode.
To change the device’s read mode, the appropriate command must be issued to the device.
the command codes used to configure the device for the desired read mode. The
following sections describe each read mode.
Table 21: Read Mode Command Bus-Cycles
Command
Read Array
Read Status Register
Read Device Information
CFI Query
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address.
9.2.1
Read Array
Upon power-up or return from reset, the device defaults to Read Array mode. Issuing the Read Array
command places the device in Read Array mode. Subsequent reads output array data
on DQ[15:0]. The device remains in Read Array mode until a different read command is
issued, or a program or erase operation is performed, in which case, the read mode is
automatically changed to Read Status.
November 2007
308551-05
Setup Write Cycle
Address Bus
Data Bus
Device Address
0050h
Setup Write Cycle
Address Bus
Data Bus
Device Address
00FFh
Device Address
0070h
Device Address
0090h
Device Address
0098h
Confirm Write Cycle
Address Bus
Data Bus
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Table 21
shows
Confirm Write Cycle
Address Bus
Data Bus
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Datasheet
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