TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Table 24: Valid Commands During Suspend (Sheet 2 of 2)
Device Command
Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Program OTP Register
During Suspend, array-read operations are not allowed in blocks being erased or
programmed.
A block-erase under program-suspend is not allowed. However, word-program under
erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-
suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.
To resume a suspended program or erase operation, issue the Resume command to
any device address. The read mode of the device is automatically changed to Read
Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes
low, and the respective Status Register bits are cleared.
When the Resume command is issued during a simultaneous erase-suspend/ program-
suspend condition, the programming operation is resumed first. Upon completion of the
programming operation, the Status Register should be checked for any errors, and
cleared. The resume command must be issued again to complete the erase operation.
Upon completion of the erase operation, the Status Register should be checked for any
errors, and cleared.
9.6
Status Signal (STS)
The STATUS (STS) signal can be configured to different states using the STS
Configuration command
remains in that configuration until another Configuration command is issued or RP# is
asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low
indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready
for a new operation or suspended.
Table 25: STS Configuration Register
Command
STS Configuration
Notes:
1.
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
2.
In case of 256 Mb device (2x128), keep the second cycle to the same address. (ie. Do not toggle A24 for the second cycle)
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is
given followed by the desired configuration code. The three alternate configurations are
all pulse mode for use as a system interrupt as described in the following paragraphs.
For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1
controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with
the Configuration command resets the STS signal to the default RY/BY# level mode.
Datasheet
42
Numonyx™ Embedded Flash Memory (J3 v. D)
Program Suspend
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
(Table
25). Once the STS signal has been configured, it
Table 26
displays possible STS configurations.
Setup Write Cycle
Address Bus
Data Bus
1
Device Address
00B8h
Erase Suspend
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Confirm Write Cycle
Address Bus
Data Bus
2
Device Address
Register Data
November 2007
308551-05