TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note:
STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
Table 26: STS Configuration Coding Definitions
D7
D6
D5
D[1:0] = STS Configuration
Codes
00 = default, level mode; device
Controls HOLD to a memory controller to prevent accessing a flash memory subsystem
ready indication
while any flash device's WSM is busy.
Generates a system interrupt pulse when any flash device in an array has completed a
01 = pulse on Erase Complete
block erase. Helpful for reformatting blocks after file system free space reclamation or
“cleanup.”
10 = pulse on Program Complete
Not supported on this device.
11 = pulse on Erase or Program
Generates system interrupts to trigger servicing of flash arrays when either erase or
Complete
program operations are completed, when a common interrupt service routine is desired.
Notes:
1.
When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.
2.
An invalid configuration code will result in both SR4 and SR5 being set.
3.
Reserved bits are invalid should be ignored.
9.7
Security and Protection
Numonyx™ Embedded Flash Memory (J3 v. D) device offer both hardware and software
security features. Block lock operations, PRs and VPEN allow users to implement
various levels of data protection.
9.7.1
Normal Block Locking
Numonyx™ Embedded Flash Memory (J3 v. D) has the unique capability of Flexible
Block Locking (locked blocks remain locked upon reset or power cycle): All blocks are
unlocked at the factory. Blocks can be locked individually by issuing the Set Block Lock
Bit command sequence to any address within a block. Once locked, blocks remain
locked when power is removed, or when the device is reset.
All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits
command sequence to any device address. Locked blocks cannot be erased or
programmed.
Table 27
Table 27: Block Locking Command Bus-Cycles
Command
Set Block Lock Bit
Clear Block Lock Bits
Notes:
1.
In case of 256 Mb device (2x128), the command should be issued to the base address of the die
2.
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
November 2007
308551-05
D4
D3
Reserved
summarizes the command bus-cycles.
Setup Write Cycle
Address Bus
Data Bus
1
Block Address
0060h
2
Device Address
0060h
D2
D1
D0
Pulse on
Pulse on Erase
Program
Complete (1)
Complete (1)
Notes
Confirm Write Cycle
Address Bus
Data Bus
Block Address
0001h
Device Address
00D0h
Datasheet
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