TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Numonyx™ Embedded Flash Memory (J3 v. D)
Figure 23: Byte/Word Program Flowchart
Start
Write 40H,
Address
Write Data and
Address
Read Status
Register
0
SR.7 =
1
Full Status
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
(See Above)
1
SR.3 =
Voltage Range Error
0
1
SR.1 =
Device Protect Error
0
1
SR.4 =
Programming Error
0
Byte/Word
Program
Successful
November 2007
308551-05
Bus
Command
Comments
Operation
Setup Byte/
Data = 40H
Write
Word Program
Addr = Location to Be Programmed
Byte/Word
Data = Data to Be Programmed
Write
Program
Addr = Location to Be Programmed
Read
Status Register Data
(Note 1)
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR full status check can be done after each program operation, or
after a sequence of programming operations.
Write FFH after the last program operation to place device in read
array mode.
Bus
Command
Comments
Operation
Check SR.3
Standby
1 = Programming to Voltage Error
Detect
Check SR.1
1 = Device Protect Detect
Standby
RP# = V
, Block Lock-Bit Is Set
IH
Only required for systems
implemeting lock-bit configuration.
Check SR.4
Standby
1 = Programming Error
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Datasheet
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