TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 


Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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Figure 28: Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read Status Register
0
SR.7 =
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.4,5 =
0
1
SR.5 =
0
Clear Block Lock-Bits
Successful
Datasheet
56
Numonyx™ Embedded Flash Memory (J3 v. D)
Bus
Operation
Write
Write
Read
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
Bus
Operation
Standby
Voltage Range Error
Standby
Command Sequence
Standby
Error
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register
command.
Clear Block Lock-Bits
If an error is detected, clear the status register before attempting retry
Error
or other error recovery.
Command
Comments
Clear Block
Data = 60H
Lock-Bits Setup
Addr = X
Clear Block or
Data = D0H
Lock-Bits Confirm
Addr = X
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Clear Block Lock-Bits Error
November 2007
308551-05