TE28F640J3D75

Manufacturer Part NumberTE28F640J3D75
ManufacturerIntel
TE28F640J3D75 datasheet
 

Specifications of TE28F640J3D75

Cell TypeNORDensity64Mb
Access Time (max)75nsInterface TypeParallel
Boot TypeNot RequiredAddress Bus23/22Bit
Operating Supply Voltage (typ)3/3.3VSync/asyncAsynchronous
Package TypeTSOPProgram/erase Volt (typ)2.7 to 3.6V
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8/16BitNumber Of Words8M/4Mword
MountingSurface MountPin Count56
Lead Free Status / Rohs StatusNot Compliant  
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2.0
Functional Overview
The Numonyx™ Embedded Flash Memory (J3 v. D) family contains high-density
memory organized in any of the following configurations:
• 32 Mbytes or 16 Mword (256-Mbit), organized as two-hundred-fifty-six 128-Kbyte
(131,072 bytes) erase blocks- Users should be aware that this density is not
offered in a monolithic part and the device is made up of 2x128-Mb devices.
• 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128-
Kbyte erase blocks
• 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks
• 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks
These devices can be accessed as 8- or 16-bit words. See
Diagram (32, 64 and 128 Mbit)” on page 10
A 128-bit Protection Register has multiple uses, including unique flash device
identification.
The Numonyx™ Embedded Flash Memory (J3 v. D) device includes new security
features that were not available on the (previous) 0.25µm and 0.18µm versions of the
J3 family. These new security features prevent altering of code through different
protection schemes that can be implemented, based on user requirements.
The Numonyx™ Embedded Flash Memory (J3 v. D) device optimized architecture and
interface dramatically increases read performance by supporting page-mode reads.
This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems
to work with all SCS-compliant flash memory devices, independent of system-level
packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS
provides the highest system/device data transfer rates and minimizes device and
system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence written to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one
second, independent of other blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software to suspend block erase to
read or program data from any other block. Similarly, program suspend allows system
software to suspend programming (byte/word program and write-to-buffer operations)
to read data or execute code from any other block that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum
programming performance. By using the Write Buffer, data is programmed in buffer
increments.
Datasheet
8
Numonyx™ Embedded Flash Memory (J3 v. D)
Figure 1, “Memory Block
for further details.
November 2007
308551-05