MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet
MC68HC912B32VFU8
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M68HC12B Family Data Sheet M68HC12 Microcontrollers M68HC12B Rev. 9.1 07/2005 freescale.com ...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...
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... Updated to meet Freescale identity guidelines. 2005 4 Description Protection Circuitry — Added subsection for clarity. FP M68HC12B Family Data Sheet, Rev. 9.1 Page Number(s) 29 305 195 195 205 205 172 313 N/A 62 197 208 N/A 307 310 315 315 316 307 310 183 Throughout Freescale Semiconductor ...
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... Chapter 13 Enhanced Capture Timer (ECT) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Chapter 14 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Chapter 15 Byte Data Link Communications (BDLC 213 Chapter 16 msCAN12 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Chapter 17 Analog-to-Digital Converter (ATD .277 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Chapter 20 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 5 ...
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... List of Chapters 6 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.6.4.1 Port 1.6.4.2 Port 1.6.4.3 Port 1.6.4.4 Port DLC 1.6.4.5 Port CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.4.6 Port 1.6.4.7 Port 1.6.4.8 Port 1.6.4.9 Port 1.6.5 Port Pullup, Pulldown, and Reduced Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Freescale Semiconductor Chapter 1 General Description M68HC12B Family Data Sheet, Rev. 9.1 7 ...
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... Clock and Watchdog Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.4 Parallel Input/Output (I/ 4.7.5 Central Processing Unit (CPU 4.7.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.7 Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.8 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8 Chapter 2 Register Block Chapter 3 Central Processor Unit (CPU) Chapter 4 Resets and Interrupts M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.3 EEPROM Control Registers 7.3.1 EEPROM Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3.2 EEPROM Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3.3 EEPROM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3.4 EEPROM Control Register Freescale Semiconductor Chapter 5 Chapter 6 Bus Control and Input/Output (I/O) Chapter 7 EEPROM M68HC12B Family Data Sheet, Rev. 9.1 9 ...
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... Real-Time Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.7.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.7.5 Arm/Reset COP Timer Register 120 10.8 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10 Chapter 8 FLASH EEPROM Chapter 9 Read-Only Memory (ROM) Chapter 10 Clock Generation Module (CGM) M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3.13 Timer Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.14 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.15 Data Direction Register for Timer Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4 Timer Operation in Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Freescale Semiconductor Chapter 11 Pulse-Width Modulator (PWM) Chapter 12 Standard Timer (TIM) M68HC12B Family Data Sheet, Rev. 9.1 11 ...
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... Pulse Accumulator B Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.4.25 8-Bit Pulse Accumulators Holding Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.4.26 Modulus Down-Counter Count Registers 187 13.4.27 Timer Input Capture Holding Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.5 Timer and Modulus Counter Operation in Different Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12 Chapter 13 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.4.2 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.4.3 Run Mode 215 15.5 Power-Conserving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.5.1 BDLC Wait and CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.5.2 BDLC Stop and CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Freescale Semiconductor Chapter 14 Serial Interface Chapter 15 M68HC12B Family Data Sheet, Rev. 9.1 13 ...
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... Valid BREAK Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.7.5 Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.8 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.1 Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.2 Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.3 Rx and Tx Shadow Registers 228 15.8.4 Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Transmit Buffer Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.12 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.12.1 msCAN12 Module Control Register 262 16.12.2 msCAN12 Module Control Register 263 16.12.3 msCAN12 Bus Timing Register 264 Freescale Semiconductor Chapter 16 msCAN12 Controller M68HC12B Family Data Sheet, Rev. 9.1 15 ...
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... Enabling BDM Firmware Commands 292 18.3.3 BDM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.3.4 BDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 18.3.5 BDM Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 18.3.5.1 Hardware Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 18.3.5.2 Firmware Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 16 Chapter 17 Analog-to-Digital Converter (ATD) Chapter 18 Development Support M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 19.16 Multiplexed Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 19.17 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 20.2 80-Pin Quad Flat Pack (Case 841B-02 332 Freescale Semiconductor Chapter 19 Electrical Specifications Chapter 20 Mechanical Specifications M68HC12B Family Data Sheet, Rev. 9.1 17 ...
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... Table of Contents 18 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Synchronous serial peripheral interface (SPI) J1850 byte data link communication (BDLC) Controller area network module (CAN) Computer operating properly (COP) watchdog timer Slow mode clock divider 80-pin quad flat pack (QFP) Single-wire background debug mode (BDM) Freescale Semiconductor MC68HC912B32 MC68HC12BE32 MC68HC912BC32 MC68HC12BC32 ...
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... External event counting – Gated time accumulation • Pulse-width modulator (PWM): – 8-bit, 4-channel or 16-bit, 2-channel – Separate control for each pulse width and duty cycle – Programmable center-aligned or left-aligned outputs 20 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... Mask sets that do not have the slow-mode clock divider feature on the MC68HC12BE32 include: H54T and J38M. Mask sets that do not have the slow-mode clock divider feature on the MC68HC(9)12BC32 include: J15G. Freescale Semiconductor (CGM). The register that controls this feature is M68HC12B Family Data Sheet, Rev. 9.1 ...
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... SDO/MOSI SPI SCK CS/SS PW0 PW1 PWM PW2 PW3 I/O I/O I/O I/O I/O DLCRx BDLC DLCTx I/O I/O I/O I/O I/O I/O Freescale Semiconductor DDA V SSA PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 ...
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... DDRA V DDX × SSX PORT A POWER FOR I/O DRIVERS WIDE BUS NARROW BUS Figure 1-2. Block Diagram for MC68HC(9)12BC32 Freescale Semiconductor 1-KBYTE RAM 768-BYTE EEPROM CONVERTER CPU12 PERIODIC INTERRUPT COP WATCHDOG CLOCK MONITOR BREAK POINTS TIMER AND ACCUMULATOR PP LITE INTEGRATION ...
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... DDA SSA allows the supply voltage to be bypassed independently. 1.6.2.4 V and and V are the reference voltage pins for the ATD Figure 1-3 M68HC12B Family Data Sheet, Rev. 9.1 and Figure 1-4 show the pin 1.6.3 Signal Descriptions. Table 1-2. Freescale Semiconductor ...
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... PORT B Notes: 1. Pin (no connect) on the MC68HC12BE32 narrow mode, high and low data bytes are multiplexed in alternate bus cycles on port A. Figure 1-3. Pin Assignments for MC68HC912B32 and MC68HC12BE32 Devices Freescale Semiconductor PORT DLC MC68HC912B32 80-PIN QFP PORT E M68HC12B Family Data Sheet, Rev. 9.1 ...
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... SSA 59 V DDA 58 PAD7 / AN7 57 PAD6 / AN6 56 PAD5 / AN5 55 PAD4 / AN4 54 PAD3 / AN3 53 PAD2 / AN2 52 PAD1 / AN1 51 PAD0 / AN0 PA7 / DATA15 / ADDR15 45 PA6 / DATA14 / ADDR14 44 PA5 / DATA13 / ADDR13 43 PA4 / DATA12 / ADDR12 42 PA3 / DATA11 / ADDR11 41 PA2 / DATA10 / ADDR10 (2) PORT A PORT E Freescale Semiconductor ...
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... In all cases, take extra care in the circuit board layout around the oscillator pins. Load capacitances shown in the oscillator circuits include all stray layout capacitances. Refer to oscillator circuits. Freescale Semiconductor 10, 47 Internal power and ground 11, 48 31, 78 External power and ground supply to pin drivers ...
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... IRQ IRQ is the maskable external interrupt request pin. It provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program 28 10 MΩ CRYSTAL XTAL EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR XTAL NC M68HC12B Family Data Sheet, Rev. 9 Freescale Semiconductor ...
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... BKGD is the single-wire background mode pin. It receives and transmits serial background debugging commands. A special self-timing protocol is used. The BKGD pin has an active pullup when configured as input; BKGD has no pullup control. Currently, the tool connection configuration shown in used. Freescale Semiconductor is not needed for normal EEPROM program PP NOTE ...
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... E-clock cycle of stretch. In expanded modes, this pin is used to enable the drive control of external buses during external reads only. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of reset in expanded modes. This pin has an active pullup during and after reset in single-chip modes. 30 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
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... RxD0 61 1. The RxCAN and TxCAN designations are for the MC68HC(9)12BC32 only. Freescale Semiconductor Table 1-3. Signal Description Summary Pulse-width modulator channel outputs External bus pins share function with general-purpose I/O ports A and B. In single-chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses ...
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... DDRS ($00D7) interface subsystems and general-purpose I/O General-purpose I/O when not enabled for input capture In/Out and output compare in the timer and pulse accumulator DDRT ($00AF) subsystem M68HC12B Family Data Sheet, Rev. 9.1 for a summary of the port signal Description Freescale Semiconductor ...
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... Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Control and Input/Output (I/O). Freescale Semiconductor (I/O). M68HC12B Family Data Sheet, Rev. 9.1 Pinout and Signal Descriptions ...
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... The ADPU bit in the ATD control register 2 (ATDCTL2) enables the A/D function. Port AD pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to 34 (BDLC). Controller. Chapter 17 Analog-to-Digital Converter M68HC12B Family Data Sheet, Rev. 9.1 (ATD). Freescale Semiconductor ...
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... S pin which is programmed as a general-purpose input. If the pin is programmed as a general-purpose output, the pullup is disconnected from the pin regardless of the state of the individual PUPSx bits. Freescale Semiconductor (PWM). Chapter 12 Standard Timer M68HC12B Family Data Sheet, Rev. 9.1 Pinout and Signal Descriptions (TIM) ...
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... PWCTL RDPP Full drive ($0054) PURDS RDPS0 Full drive ($00DB) PURDS RDPS1 Full drive ($00DB) PURDS RDPS2 Full drive ($00DB) TMSK2 RDPT Full drive ($008D) DLCSCR DLCRDV Full drive ($00FD) — — — Full drive Freescale Semiconductor ...
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U2 MC34064 2 1 RSET GROUND Y1 R14 C2 C1 R32 4.7 K RESET JP1 1 1 GND HEADER ...
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MC34064 DD0 DD1 V 78 RSET IN DDX0 V DDX0 V 31 DDX1 V V DDX1 DDAD SS0 48 V GROUND SS1 ...
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... Port E data direction register, DDRE In peripheral mode, these registers are not in the map: • Mode register, MODE • Pullup control register, PUCR • Reduced drive register, RDRIV Freescale Semiconductor Figure 2-1. For additional information, refer to Mapping. NOTE M68HC12B Family Data Sheet, Rev. 9.1 Chapter 5 39 ...
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... PB3 PB2 PB1 DDA4 DDA3 DDA2 DDA1 DDB4 DDB3 DDB2 DDB1 PD4 PD3 PD2 PD1 DDE4 DDE3 DDE2 NECLK LSTRE RDWE ESTR IVIS EBSWAI PUPE PUPB RDPE RDPB Reserved U = Unaffected Freescale Semiconductor Bit 0 PA0 U PB0 U DDA0 0 DDB0 PD0 EME 1 PUPA 0 RDPA ...
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... Highest Priority I Interrupt Register $001F (HPRIO) See page 71. Breakpoint Control Register 0 $0020 (BRKCT0) See page 301. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: RAM15 RAM14 RAM13 Write: Reset ...
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... PCLK0 PPOL3 PPOL2 PPOL1 PWEN3 PWEN2 PWEN1 Bit 4 Bit 3 Bit 2 Bit Bit 4 Bit 3 Bit 2 Bit Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 BK0RW 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit PCKB0 0 PPOL0 0 PWEN0 0 Bit 0 0 Bit 0 0 Bit 0 0 ...
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... PWM Channel Duty Register 0 $0050 (PWDTY0) See page 135. PWM Channel Duty Register 1 $0051 (PWDTY1) See page 135. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: Bit 7 Bit 6 Bit 5 Write: Reset ...
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... Bit 4 Bit 3 Bit 2 Bit Bit 4 Bit 3 Bit 2 Bit PSWAI CENTR RDPP PUPP PP4 PP3 PP2 PP1 DDP4 DDP3 DDP2 DDP1 ASCIE FRZ1 PRS4 PRS3 PRS2 PRS1 Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 0 1 Bit 0 1 PSBCK PP0 U DDP0 ASCIF 0 FRZ0 0 PRS0 1 ...
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... ATD Result Register 1 $0073 (ADRx1L) See page 286. ATD Result Register 2 $0074 (ADRx2H) See page 286. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: S8CM SCAN Write: Reset ...
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... Bit 12 Bit 11 Bit 10 Bit 9 Undefined Bit 4 Bit 3 Bit 2 Bit 1 Undefined Bit 12 Bit 11 Bit 10 Bit 9 Undefined Bit 4 Bit 3 Bit 2 Bit 1 Undefined IOS4 IOS3 IOS2 IOS1 Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 IOS0 0 ...
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... Timer Mask Register 1 $008C (TMSK1) See page 146. Timer Mask Register 2 $008D (TMSK2) See page 147. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Freescale Semiconductor Bit Read: FOC7 FOC6 FOC5 Write: Reset ...
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... Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 C0F Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 ...
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... Pulse Accumulator Count $00A5 Register 0 (PACN0) See page 178. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 10 of 19) Freescale Semiconductor Bit Read: Bit 15 Bit 14 Bit 13 Write: Reset: ...
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... DLY1 NOVW4 NOVW3 NOVW2 NOVW1 HS04 TFMOD PACMX BUFEN TCBYP PT4 PT3 PT2 PT1 DDT4 DDT3 DDT2 DDT1 PBOV PBOV Bit 4 Bit 3 Bit 2 Bit Reserved U = Unaffected Freescale Semiconductor Bit 0 MCPR0 0 POLF0 0 PA0EN 0 DLY0 0 NOVW0 0 LATQ 0 R (1) PCBYP 0 PT0 0 DDT0 Bit 0 0 ...
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... Timer Input Capture Holding $00BE Register 3 (TC3H) See page 188. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 12 of 19) Freescale Semiconductor Bit Read: Bit 7 Bit 6 Bit 5 Write: ...
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... SBR12 SBR11 SBR10 SBR9 SBR4 SBR3 SBR2 SBR1 WAKE ILT ILIE TE RE RWU IDLE R4T4 R3T3 R2T2 R1T1 Unaffected by reset MSTR CPOL CPHA SSOE PUPS RDS Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 0 0 SBR8 0 SBR0 SBK RAF R0T0 R R LSBF 0 SPC0 0 ...
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... Reserved ↓ $00EF Reserved EEPROM Configuration Register $00F0 (EEMCR) See page 94. Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 14 of 19) Freescale Semiconductor Bit Read Write: Reset Read: ...
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... EECPD EECPRD 0 EECPM BYTE ROW ERASE EELAT FENLV FDISVFP VTCK STRE FEESWAI SVFP ERAS LAT NBFS TEOD TSIFR TMIFR1 BD4 BD3 BD2 BD1 0 BO3 BO2 BO1 Reserved U = Unaffected Freescale Semiconductor Bit EEPGM 0 LOCK 0 BOOTP 1 MWPR 0 ENPE 0 WCM TMIFR0 0 BD0 BO0 1 ...
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... Identifier Acceptance (3) $0108 Control Register (CIDAC) See page 270. $0109 Reserved ↓ Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 16 of 19) Freescale Semiconductor Bit Read Write: Reset ...
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... AM3 AM2 AM1 Unaffected by reset AM4 AM3 AM2 AM1 Unaffected by reset AC4 AC3 AC2 AC1 Unaffected by reset AC4 AC3 AC2 AC1 Unaffected by reset R = Reserved U = Unaffected Freescale Semiconductor Bit 0 R RXERR0 0 TXERR0 0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 ...
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... See page 276. $0140 ↓ $014F $0150 ↓ $015F Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 18 of 19) Freescale Semiconductor Bit Read: AC7 AC6 AC5 Write: Reset: Read: AC7 ...
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... Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1. Register Map (Sheet 19 of 19) 58 Bit TRANSMIT BUFFER 1 (TX1) TRANSMIT BUFFER 2 (Tx2) = Unimplemented R M68HC12B Family Data Sheet, Rev. 9 (3) — SEE 16.3.3 Transmit Structures (3) — SEE 16.3.3 Transmit Structures = Reserved U = Unaffected Freescale Semiconductor Bit 0 ...
Page 59
... The CPU12 also offers an extensive set of indexed addressing capabilities. 3.2 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. See Figure 3- Freescale Semiconductor 8-BIT ACCUMULATORS A AND 16-BIT DOUBLE ACCUMULATOR INDEX REGISTER X Y ...
Page 60
... D14 D13 D12 (A7) (A6) (A5) (A4) Write: Reset Unaffected by reset Figure 3-2. Accumulator A ( Unaffected by reset Figure 3-3. Accumulator B (B) NOTE Figure 3-4. Accumulator D ( D11 D10 (A3) (A2) (A1) (A0) (B7) Unaffected by reset M68HC12B Family Data Sheet, Rev. 9 Bit Bit (B6) (B5) (B4) (B3) (B2) Freescale Semiconductor 1 Bit (B1) (B0) ...
Page 61
... The stack pointer can also serve as a temporary data storage location index register for indexed addressing. The LDS and STS instructions can be used to manipulate data in and out of the stack pointer. Bit Read: SP15 SP14 SP13 SP12 Write: Reset: Freescale Semiconductor NOTE Figure 3-5. Index Register X ( X11 X10 Unaffected by reset NOTE Figure 3-6 ...
Page 62
... C — Carry/Borrow Flag The C flag is set when an addition or subtraction operation produces a carry or borrow. 62 Figure 3-8. Program Counter (PC SP11 SP10 SP9 SP8 SP7 Unaffected by reset M68HC12B Family Data Sheet, Rev. 9 SP6 SP5 SP4 SP3 SP2 2 1 Bit Freescale Semiconductor 1 Bit 0 SP1 SP0 ...
Page 63
... Indexed INST abd,xysp accumulator offset Indexed INST oprx9,xysp 9-bit offset Indexed INST oprx16,xysp 16-bit offset Freescale Semiconductor Table 3-1. Addressing Mode Summary Abbreviation INH Operands (if any) are in CPU registers. Operand is included in instruction stream or IMM 8- or 16-bit size implied by context. Operand is the lower 8 bits of an address in the range DIR $0000– ...
Page 64
... Auto post-decrement/increment; n,+ pre-(0) or post-(1 –8 to – n,r+ rr can specify (PC not a valid choice) Accumulator offset (unsigned 8-bit or 16-bit) aa: (16-bit see accumulator D offset indexed-indirect rr can specify Accumulator D offset indexed-indirect rr can specify M68HC12B Family Data Sheet, Rev. 9.1 Description Freescale Semiconductor ...
Page 65
... To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data. Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 Opcodes and Operands 65 ...
Page 66
... Central Processor Unit (CPU) 66 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 67
... Interrupt vectors are not affected by priority assignment. HPRIO can be written only while the I bit is set (interrupts inhibited). of priority for all devices except the MC68HC(9)12BC32. for the MC68HC(9)12BC32. Freescale Semiconductor Table 4-1 lists interrupt sources and vectors in default order Table 4-2 M68HC12B Family Data Sheet, Rev ...
Page 68
... COP rate selected — None — None — None — IRQEN $F2 RTIE $F0 C0I $EE C1I $EC C2I $EA C3I $E8 C4I $E6 C5I $E4 C6I $E2 C7I $E0 TOI $DE PAOVI $DC PAI $DA SPIE $D8 TIE, TCIE, RIE, ILIE $D6 — $D4 ASCIE $D2 IE $D0 — $80–$C0 — $C2–$C8 PBOVI $CA MCZI $CC — $CE Freescale Semiconductor ...
Page 69
... MSCAN wakeup $FFCA–$FFCF Reserved (not implemented) $FFC8–$FFC9 MSCAN errors $FFC6, $FFC7 MSCAN receive $FFC4, $FFC5 MSCAN transmit $FF80, $FFC3 Reserved (implemented) Freescale Semiconductor Local Enable CCR Mask Register None None None COPCTL None None None ...
Page 70
... DLY can be written once in normal modes. In special modes, DLY can be written anytime. The delay time of about 4096 cycles is based on the E-clock rate Stabilization delay on exit from stop mode stabilization delay on exit from stop mode IRQEN DLY M68HC12B Family Data Sheet, Rev. 9 Bit Freescale Semiconductor ...
Page 71
... COPRST register to keep a watchdog timer from timing out. Other instructions may be executed between these writes. A write of any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset to occur. Freescale Semiconductor 6 5 ...
Page 72
... After reset, the internal register block is located at $0000–$01FF, the register-following space is at $0200–$03FF, and RAM is at $0800–$0BFF. EEPROM is located at $0D00–$0FFF. FLASH EEPROM/ROM is located at $8000–$FFFF in single-chip modes and at $0000–$7FFF (but disabled) in expanded modes. 72 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 73
... However, the CPU then: • Adjusts the stack pointer to point again at the stacked CCR location, SP – 9 • Fetches the vector of the pending interrupt • Begins execution of the interrupt service routine at the location pointed to by the vector Freescale Semiconductor Stacked Values RTN SP – – – ...
Page 74
... Resets and Interrupts 74 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 75
... Special modes — Protected control registers and bits are allowed greater access for special purposes such as testing and emulation. A system development and debug feature, background debug mode (BDM) is available in all modes. In special single-chip mode, BDM is active immediately after reset. Freescale Semiconductor Table 5-1. Mode Selection Mode Special single chip ...
Page 76
... BKGD pin. There are no external address and data buses in this mode. The MCU operates as a stand-alone device and all program and data space are on-chip. External port pins can be used for general-purpose I/O. 76 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 77
... When active, BDM ROM takes precedence over other resources, although a conflict between BDM ROM and register space is not possible. precedence. In expanded modes, all address space not utilized by internal resources is by default external memory. Freescale Semiconductor for more details. Table 5-2 M68HC12B Family Data Sheet, Rev. 9.1 ...
Page 78
... MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special peripheral and reserved modes cannot be selected. 78 Table 5-2. Mapping Precedence Resource 1 BDM ROM (if active) 2 Register space 3 RAM 4 EEPROM 5 FLASH EEPROM/ROM 6 External memory MODB MODA ESTR Figure 5-1. Mode Register (MODE) M68HC12B Family Data Sheet, Rev. 9 Bit 0 IVIS EBSWAI 0 EME Freescale Semiconductor ...
Page 79
... PORTE and DDRE removed from the memory map (expanded mode PORTE and DDRE in the memory map Normal modes: Write once Special modes: Write anytime except the first time Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 Mode and Resource Mapping Registers 79 ...
Page 80
... Write: Once in normal modes; anytime in special modes RAM15–RAM11 — RAM Position Bits These bits specify the upper five bits of the 16-bit RAM address REG13 REG12 REG11 RAM14 RAM13 RAM12 RAM11 M68HC12B Family Data Sheet, Rev. 9 Bit MMSWAI Bit Freescale Semiconductor ...
Page 81
... The 32-Kbyte FLASH EEPROM/ROM can be mapped to either the upper or lower half of the 64-Kbyte address space. When mapping conflicts occur, registers, RAM, and EEPROM have priority over FLASH EEPROM. Only the MC68HC912B32 contains FLASH EEPROM. The MC68HC12BE32 contains ROM. To use memory expansion, the part must be operated in one of the expanded modes. Freescale Semiconductor EE14 ...
Page 82
... These bits determine the amount of clock stretch on accesses to the external address space. In single-chip and peripheral modes, these bits have no meaning or effect. Table 5-4. Expanded Stretch Bit Function EXSTR1 and EXSTR0 RFSTR1 RFSTR0 EXSTR1 5-3. E Clocks Stretched Clocks Stretched M68HC12B Family Data Sheet, Rev. 9 Bit 0 EXSTR0 MAPROM ROMON Freescale Semiconductor ...
Page 83
... VECTORS $FFFF EXPANDED Freescale Semiconductor VECTORS VECTORS SINGLE-CHIP SINGLE-CHIP NORMAL SPECIAL Figure 5-6. Memory Map M68HC12B Family Data Sheet, Rev. 9.1 Memory Map $0000 ...
Page 84
... Operating Modes and Resource Mapping 84 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 85
... In any expanded mode, port E pins may be needed for bus control (for example, ECLK and R/W). To regain the single-chip functions of port E, the emulate port E (EME) control bit in the MODE register may Freescale Semiconductor Table 6-1. Detecting Access Type R/W Type of Access ...
Page 86
... ADDR13 ADDR12 DATA14/6 DATA13/5 DATA12 DDA6 DDA5 DDA4 DDA3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 PA3 PA2 PA1 PA0 ADDR11 ADDR10 ADDR9 ADDR8 DATA11 DATA10 DATA9 DATA8 ADDR11 ADDR10 ADDR9 ADDR8 DATA11/3 DATA10/2 DATA9/1 DATA8 Bit 0 DDA2 DDA1 DDA0 Freescale Semiconductor ...
Page 87
... Write: Anytime, if register is in the map This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes Associated pin is an output Associated pin is a high-impedance input. Freescale Semiconductor PB6 ...
Page 88
... Associated pin is an output Associated pin is a high-impedance input PE6 PE5 PE4 PE3 MODB or MODA or LSTRB or ECLK IPIPE1 IPIPE0 TAGLO DDE6 DDE5 DDE4 DDE3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 PE2 PE1 PE0 R/W IRQ XIRQ 2 1 Bit DDE2 Freescale Semiconductor ...
Page 89
... In peripheral mode, the PEAR register is not accessible for reads or writes. NDBE — No Data Bus Enable Bit Normal: Write once Special: Write anytime except the first time 1 = PE7 used for general-purpose I PE7 used for external control of data enables on memories Freescale Semiconductor CGMTE ...
Page 90
... This bit has no effect in single-chip modes PE2 configured as R/W pin 0 = PE2 configured as general-purpose I/O pin R/W is used for external writes. After reset in normal expanded mode disabled. If needed, it should be enabled before any external writes. 90 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 91
... This bit has no effect if port B is used as part of the address/data bus (pullups are inactive). PUPA — Pullup Port A Enable Bit 0 = Disable port A pullups 1 = Enable pullups for all port A input pins This bit has no effect, if port A is used as part of the address/data bus (pullups are inactive). Freescale Semiconductor ...
Page 92
... Reduced drive for all port B output pins 0 = Full drive for all port B output pins RDPA — Reduced Drive of Port A Bit 1 = Reduced drive for all port A output pins 0 = Full drive for all port A output pins RDPE M68HC12B Family Data Sheet, Rev. 9 Bit 0 0 RDPB RDPA Freescale Semiconductor ...
Page 93
... However, the EEPGM control bit will remain set. When stop mode is terminated, the program/erase voltage will be turned back on automatically if EEPGM is set. Freescale Semiconductor Figure 7-1). For information on remapping the register block and Chapter 5 Operating Modes and Resource M68HC12B Family Data Sheet, Rev ...
Page 94
... The RC oscillator is required when the system bus clock is lower than f Read and write anytime. 94 $_D00 BPROT4 256 BYTES $_E00 BPROT3 256 BYTES $_F00 BPROT2 128 BYTES $_F80 BPROT1 $_FC0 BPROT0 M68HC12B Family Data Sheet, Rev. 9 Bit 0 EESWAI PROTLCK EERC PROG Freescale Semiconductor ...
Page 95
... Bulk program/erase all odd rows. Refers to a physical location in the array rather than an odd byte address EEVEN — Even Row Programming Bit 0 = Even row bulk programming/erasing is disabled Bulk program/erase all even rows. Refers to a physical location in the array rather than an even byte address. Freescale Semiconductor ...
Page 96
... BYTE and ROW have no effect when ERASE = 0. BYTE pin BYTE ROW Table 7-2. Erase Selection ROW Block Size 0 Bulk erase entire EEPROM array 1 Row erase 32 bytes 0 Byte or aligned word erase 1 Byte or aligned word erase M68HC12B Family Data Sheet, Rev. 9 Bit 0 ERASE EELAT EEPGM Freescale Semiconductor ...
Page 97
... Write EEPGM = 1. 4. Wait for programming ( t PROG 5. Write EEPGM = 0 and EELAT = 0. To program/erase more bytes or words without intermediate EEPROM reads, only write EEPGM = 0 in step 5, leaving EELAT = 1, and jump to step 2. Freescale Semiconductor NOTE ) or erase ( ) delay time. t Erase M68HC12B Family Data Sheet, Rev. 9.1 ...
Page 98
... EEPROM 98 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 99
... FLASH EEPROM Registers A 4-byte register block controls the FLASH EEPROM module operation. Configuration information is specified and programmed independently from the contents of the FLASH EEPROM array. At reset, the 4-byte register section starts at address $00F4. Freescale Semiconductor NOTE Mapping. M68HC12B Family Data Sheet, Rev. 9.1 ...
Page 100
... FSTE — Stress Test Enable Bit 0 = Disables the gate/drain stress circuitry 1 = Enables the gate/drain stress circuitry 100 GADR HVT FENLV FDISVFP M68HC12B Family Data Sheet, Rev. 9 Bit LOCK Bit BOOTP Bit 0 VTCK STRE MWPR Freescale Semiconductor ...
Page 101
... ADDR1 and ADDR0 = 00, along with the word location addressed if ADDR1 and ADDR0 = 10, will both be programmed with the same word data from the programming latches. This bit should not be changed during programming Multiple word programming disabled 1 = Program 32 bits of data Freescale Semiconductor Voltage Lock Bit FP pin low ...
Page 102
... Status of ERAS cannot change if Table 8-1 for the effects of LAT on array reads. A high pin will prevent assertion of the LAT bit when the programming voltage FP M68HC12B Family Data Sheet, Rev. 9 Bit 0 ERAS LAT ENPE Table 8-1 for more Freescale Semiconductor ...
Page 103
... The next write to any valid address to the array after LAT is set will cause the address and data to be latched into the programming latches. Once the address and data are latched, write accesses to the array will be ignored while LAT is set. Writes to the control registers will occur normally. Freescale Semiconductor ERAS Result of Read — ...
Page 104
... V FP power supply with the programming Programming can also be accomplished FP DD pin. FP M68HC12B Family Data Sheet, Rev. 9.1 (t for erasing) PPULSE EPULSE ), the program margin pulses PPULSE ). VPROG ). VERASE pin and should be at the FP ) from the can DD Freescale Semiconductor ...
Page 105
... Read the address location to verify that it remains programmed. 12. Clear LAT. 13. If there are more locations to program, repeat steps 2 through 10. 14. Turn off V . Reduce voltage The flowchart in Figure 8-5 demonstrates the recommended programming sequence. Freescale Semiconductor pin PPULSE . VPROG , has been reached. PP pin to V ...
Page 106
... PP NO YES DATA CORRECT? NO YES LOCATION FAILED CLEAR LAT DONE? NO YES TURN OFF V FP DONE PROG Figure 8-5. Program Sequence Flow M68HC12B Family Data Sheet, Rev. 9.1 SET MARGIN FLAG INCREMENT n COUNTER PP READ LOCATION DATA CORRECT? YES 50 YES TO PROGRAM Freescale Semiconductor ...
Page 107
... If all of the FLASH EEPROM locations are erased, repeat the same number of pulses as required to erase the array. This provides 100 percent erase margin. 11. Read the entire array to ensure that the FLASH EEPROM is erased. 12. Clear LAT. 13. Turn off V . Reduce voltage The flowchart in Figure 8-6 demonstrates the recommended erase sequence. Freescale Semiconductor pin EPULSE . VERASE pin M68HC12B Family Data Sheet, Rev ...
Page 108
... MARGIN FLAG READ NO SET? ARRAY YES DECREMENT ARRAY n COUNTER EP ERASED YES ARRAY ERASED? NO YES CLEAR LAT TURN OFF V FP ARRAY ERASED ARRAY FAILED TO ERASE Figure 8-6. Erase Sequence Flow M68HC12B Family Data Sheet, Rev. 9.1 SET MARGIN FLAG YES YES Freescale Semiconductor ...
Page 109
... The FLASH EEPROM module will operate normally, even if SMOD is asserted, until a special test function is invoked. The test mode adds additional features over normal mode. These features allow the tests to be performed even after the device is installed in the final product. Freescale Semiconductor FP NOTE M68HC12B Family Data Sheet, Rev ...
Page 110
... FLASH EEPROM 110 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 111
... After reset, the ROM array is located from addresses $8000 to $FFFF in single-chip mode. In expanded modes, the ROM array is located from address $0000 to $7FFF; however disabled from the memory map. The ROM can be mapped to an alternate address range. See Resource Mapping. Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 Chapter 5 Operating Modes and 111 ...
Page 112
... Read-Only Memory (ROM) 112 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 113
... MC68HC(9)12BC32 include: J15G. 10.2 Block Diagram EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCILLATOR OUT ÷ 2 Freescale Semiconductor NOTE SLOW P CLOCK SLOW MODE CLOCK DIVIDER SLOW E CLOCK E AND P CLOCK GENERATOR T CLOCK GENERATOR Figure 10-1. CGM Block Diagram M68HC12B Family Data Sheet, Rev. 9.1 ...
Page 114
... Read: Bit 7 Bit 6 Bit 5 Write: Reset Read Write: Reset Unimplemented Figure 10-2. CGM Register Map M68HC12B Family Data Sheet, Rev. 9 RTBYP RTR2 RTR1 FCOP DISR CR2 CR1 Bit 4 Bit 3 Bit 2 Bit SLDV2 SLDV1 Freescale Semiconductor Bit 0 RTR0 CR0 1 Bit 0 0 SLDV0 0 ...
Page 115
... Driven by slow clock divider in wait mode. Drives on-chip peripherals except BDLC and timer. 2. Remains at oscillator divided by 2 rate in wait mode. Drives BDLC and timer. Figure 10-4. Internal Clock Relationships in Wait Mode Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 Clock Selection and Generation ...
Page 116
... This timeout is based delay so that the clock monitor can operate without any MCU clocks. Clock monitor timeouts are shown in 116 NOTE Table 10-1. Table 10-1. Clock Monitor Timeout Supply 5 V ± 10% M68HC12B Family Data Sheet, Rev. 9.1 Range 2–20 µs Freescale Semiconductor ...
Page 117
... The range of the divider 128 by steps of power of 2. When the bits are clear, the divider is bypassed. Table 10-2 shows the divider for all bit conditions and the resulting bus rate for three example oscillator frequencies. Table 10-2. Slow Mode Register Divider Rates SLDV2 SLDV1 Freescale Semiconductor Bus Rate Divider SLDV0 (16-MHz Oscillator) 0 Off 8 MHz ...
Page 118
... Table 10-3. Real-Time Interrupt Rates Timeout Period Divide E By 4.0 MHz 0 OFF OFF 13 1 2.048 4.096 8.196 16.384 32.768 65.536 131. M68HC12B Family Data Sheet, Rev. 9 Bit 0 RTR2 RTR1 RTR0 Timeout Period E = 8.0 MHz OFF 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms Freescale Semiconductor 13 , ...
Page 119
... STOP. Always keep FCME = 0, if STOP will be used. FCM — Force Clock Monitor Reset Bit Writes are not allowed in normal modes, anytime in special modes. If DISR is set, this bit has no effect Normal operation 1 = Force a clock monitor reset, if clock monitor is enabled. Freescale Semiconductor ...
Page 120
... Bit 6 Bit 5 Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9.1 . (RTBYP in the RTICTL register allows all 8.0-MHz Timeout 0 to +1.024 ms OFF 1.024 ms 4.096 ms 16.384 ms 65.536 ms 262.144 ms 524.288 ms 1.048576 Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 121
... SCI0 RECEIVE BAUD RATE (16x) ÷ SCI0 TRANSMIT BAUD RATE (1x) Figure 10-10. Clock Chain for SCI, BDLC, RTI, and COP Freescale Semiconductor 10-12, and Figure 10-13 summarize the clock divider chains for these ÷ ÷ REGISTER: RTICTL BIT: RTBYP ...
Page 122
... BITS: PAEN, CLK1, AND CLK0 0:x:x 1:0:0 1:0:1 1:1:0 PACLK/256 1:1:1 PACLK/65536 (PAOV) PULSE ACC HIGH BYTE TO TIM COUNTER MODULUS DOWN REGISTER: PACTL BITS: PAEN, CLK1, AND CLK0 0:x:x 1:0:0 1:0:1 1:1:0 PACLK/256 1:1:1 PACLK/65536 (PAOV) TO TIMER ACC MAIN COUNTER Freescale Semiconductor ...
Page 123
... Figure 10-13. Clock Chain for SPI, ATD, and BDM Freescale Semiconductor ÷ 2 SPI BIT RATE E CLOCK BKGD IN SYNCHRONIZER BKGD DIRECTION BKGD PIN BKGD OUT LOGIC M68HC12B Family Data Sheet, Rev. 9.1 Clock Divider Chains ...
Page 124
... Clock Generation Module (CGM) 124 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 125
... The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes precedence over the general-purpose port. When PWM outputs are not in use, the port pins may be used for discrete input/output. Freescale Semiconductor 11-2, and Figure 11-3. ...
Page 126
... PWDTYx PERIOD 8-BIT COMPARE = PWPERx (PWPER − PWDTY) × PWPER 2 M68HC12B Family Data Sheet, Rev. 9.1 FROM PORT P DATA REGISTER S Q MUX MUX Q R PPOLx FROM PORT P DATA REGISTER T Q MUX MUX Q PPOLx × 2 PWDTY Freescale Semiconductor TO PIN DRIVER TO PIN DRIVER ...
Page 127
... BITS: REGISTER: PCKB2, PWPRES PCKB1, PCKB0 *CLOCK S0 = (CLOCK A)/2, (CLOCK A)/4, (CLOCK A)/6,... (CLOCK A)/512 **CLOCK S1 = (CLOCK B)/2, (CLOCK B)/4, (CLOCK B)/6,... (CLOCK B)/512 Freescale Semiconductor CLOCK A 0:0:0 8-BIT DOWN COUNTER 0:0:1 PWSCNT0 0:1:0 8-BIT SCALE REGISTER 0:1:1 PWSCAL0 1:0:0 ...
Page 128
... Table 11-1. Clock A and Clock B Prescaler PCKA2 (PCKB2 128 CON01 PCKA2 PCKA1 PCKA0 Table 11-1. Table 11-1. PCKA1 (PCKB1) PCKA0 (PCKB0 M68HC12B Family Data Sheet, Rev. 9 Bit 0 PCKB2 PCKB1 PCKB0 Value of Clock A ( ÷ ÷ ÷ ÷ ÷ ÷ ÷ 128 Freescale Semiconductor ...
Page 129
... Depending on the polarity bit, the duty registers may contain the count of either the high time or the low time. If the polarity bit is 0 and left alignment is selected, the duty registers contain a count of the low time. If the polarity bit is 1, the duty registers contain a count of the high time. Freescale Semiconductor 6 5 ...
Page 130
... Channel 1 enabled PWEN0 — PWM Channel 0 Enable Bit The pulse modulated signal will be available at port P bit 0 when its clock source begins its next cycle Channel 0 disabled 1 = Channel 0 enabled 130 PWEN3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 PWEN2 PWEN1 PWEN0 Freescale Semiconductor ...
Page 131
... When PWSCAL0 = $FF, clock A is divided by 256 then divided by two to generate clock S0. 11.2.6 PWM Scale Counter 0 Value Address: $0045 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 11-9. PWM Scale Counter Register 0 (PWSCNT0) Read: Anytime PWSCNT0 is a down-counter that, upon reaching $00, loads the value of PWSCAL0. Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit ...
Page 132
... Figure 11-11. PWM Scale Counter 1 Value (PWSCNT1) Read: Anytime PWSCNT1 is a down-counter that, upon reaching $00, loads the value of PWSCAL1. 132 Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 133
... The duty register changes the state of the output during the period to determine the duty. When a channel is enabled, the associated PWM counter starts at the count in the PWCNTx register using the clock selected for that channel. In special mode, when DISCP = 1 and is configured for left-aligned output, a match of period does not reset the associated PWM counter. Freescale Semiconductor ...
Page 134
... Period = Channel-Clock-Period × PWPER × 2(CENTR = 1) 134 Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 135
... Left-aligned output mode (CENTR = 0): Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%(PPOLx = 1) Duty cycle = [(PWPERx − PWDTYx) / (PWPERx + 1)] × 100%(PPOLx = 0) Center-aligned output mode (CENTR = 1): Duty cycle = [(PWPERx − PWDTYx) / PWPERx] × 100%(PPOLx = 0) Duty cycle = (PWDTYx / PWPERx) × 100%(PPOLx = 1) Freescale Semiconductor Bit 6 ...
Page 136
... Enable pullups for all port P input pins. PSBCK — PWM Stops While in Background Mode Bit 0 = Allows PWM to continue while in background mode 1 = Disable PWM input clock while in background mode. 136 PSWAI CENTR Unimplemented M68HC12B Family Data Sheet, Rev. 9 Bit 0 RDPP PUPP PSBCK Freescale Semiconductor ...
Page 137
... When configured as input, a read returns the pin level. When configured as output, a read returns the latched output data. A write drives associated pins only if configured for output and the corresponding PWM channel is not enabled. After reset, all pins are general-purpose, high-impedance inputs. Freescale Semiconductor ...
Page 138
... Table 11-2. PWM Boundary Conditions PWPERx PPOLx >$00 1 >$00 0 — 1 — 0 $00 1 $00 0 NOTE PERIOD HIGH TIME = DUTY CYCLE HIGH TIME Figure 11-28. Example Waveform M68HC12B Family Data Sheet, Rev. 9 Bit 0 DDP2 DDP1 DDP0 Output Low High High Low High Low Freescale Semiconductor ...
Page 139
... Equipment For this exercise, use the M68HC912B32EVB emulation board. Freescale Semiconductor Using the Output Compare 7 Feature to Generate a PWM Table 11-3. PWM Period Calculations High-Time Values Decimal Count 32 64 128 256 512 1024 ...
Page 140
... Enable OC7 to set output compare 5 pin high(OC7D). ; Load TC7 with "PERIOD" of the PWM ; Load TC5 with "HIGH TIME" of the PWM. ; Enable Timer, Timer runs during wait state, ; and while in Background Mode, also clear flags ; normally. ; Return from Subroutine M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 141
... Reset: 0 Figure 12-1. Timer Input Capture/Output Compare Select Register (TIOS) Read: Anytime Write: Anytime IOS7–IOS0 —Input Capture or Output Compare Channel Designator Bits 0 = Corresponding channel acts as an input capture Corresponding channel acts as an output compare. Freescale Semiconductor IOS6 IOS5 IOS4 IOS3 ...
Page 142
... BUFFER LATCH Figure 12-2. Timer Block Diagram M68HC12B Family Data Sheet, Rev. 9.1 TCTL1 AND TCTL2 FUNCTION, DIRECTION, AND POLARITY CTL IC INPUT TIMPT PIN PAD LOGIC OC OUTPUT POLARITY CTL TC7 INPUT TC7 PIN PIN PAD LOGIC MODULE 64 CLOCK Freescale Semiconductor ...
Page 143
... OC7M, the corresponding data bit in OC7D is stored to the corresponding bit of the timer port. When the OC7Mn bit is set, a successful OC7 action will override a successful OC6–OC0 compare action during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit. Freescale Semiconductor ...
Page 144
... Allows timer to continue running during wait 1 = Disables timer when MCU is in wait mode 144 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit TSWAI TSBCK TFFCA M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit Freescale Semiconductor ...
Page 145
... These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare (see becomes an output tied to OCn regardless of the state of the associated DDRT bit. Table 12-1. Compare Result Output Action OMn Freescale Semiconductor NOTE OL7 OM6 OL6 ...
Page 146
... Configuration 0 Capture disabled 1 Capture on rising edges only 0 Capture on falling edges only 1 Capture on any edge (rising or falling C6I C5I C4I C3I M68HC12B Family Data Sheet, Rev. 9 Bit 0 EDG5A EDG4B EDG4A Bit 0 EDG1A EDG0B EDG0A Table 12- Bit 0 C2I C1I C0I Freescale Semiconductor ...
Page 147
... These three bits specify the number of ÷2 stages that are to be inserted between the module clock and the timer counter. See Table PR2 The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal 0. Freescale Semiconductor PUPT RDPT TCRE 12-3. ...
Page 148
... Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. For additional information, see the TCRE control bit explanation found in 12.3.7 Timer Interrupt Mask 148 C6F C5F C4F C3F Registers. M68HC12B Family Data Sheet, Rev. 9 Bit 0 C2F C1F C0F Bit Freescale Semiconductor ...
Page 149
... Write: Reset: 0 Figure 12-17. Timer Input Capture/Output Compare Register 1 (TC1) Address: $0094 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $0095 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 12-18. Timer Input Capture/Output Compare Register 2 (TC2) Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 ...
Page 150
... Bit 4 Bit Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 151
... Pulse Accumulator Control Register Address: $00A0 Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-24. Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit ...
Page 152
... Interrupt requested if PAIF is set 152 Table 12-4. Clock Selection Selected Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 153
... Figure 12-26. 16-Bit Pulse Accumulator Count Register (PACNT) Read: Anytime Write: Anytime Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Freescale Semiconductor ...
Page 154
... PT6 PT5 PT4 PT3 I/OC6 I/OC5 I/OC4 I/OC3 NOTE M68HC12B Family Data Sheet, Rev. 9 Bit 0 0 TCBYP PCBYP Bit 0 PT2 PT1 PT0 I/OC2 I/OC1 I/OC0 Freescale Semiconductor ...
Page 155
... Wait — Counters keep running, unless TSWAI = 1. Normal — Timer keeps running, unless TEN = 0. TEN = 0 —All timer operations are stopped, registers may be accessed. Gated pulse accumulator ÷64 clock is also disabled. PAEN = 0 —All pulse accumulator operations are stopped. Registers may be accessed. Freescale Semiconductor DDT6 ...
Page 156
... A comment line is deliminted by a semi-colon. If there is no code before comment, an “;” must be placed in the first column to avoid assembly errors. 156 1 ms NUMBER OF CLOCKS = THEREFORE, #CLOCKS = (2 MHz) * (0.5 ms) = 1024 = $0400 0.5 ms Figure 12-30. Example Waveform NOTE M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 157
... STD TC2H BRA CLEARFLG RTS END Freescale Semiconductor Using the Output Compare Function to Generate a Square Wave ; 16K On-Board RAM, User code data area, ; start main program at $7000 ; Subroutine used to initialize the timer: ; Output compare channel, no interrupts ; Subroutine to generate square wave ...
Page 158
... Standard Timer (TIM) 158 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 159
... Four 8-bit pulse accumulators are associated with the four buffered IC channels. Each pulse accumulator has a holding register to memorize their value by an action on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 159 ...
Page 160
... In queue mode, reads of the holding register will latch the corresponding pulse accumulator value to its holding register. 160 M68HC12B Family Data Sheet, Rev. 9.1 13.3.1 IC Channels). This will 13.3.1 IC Channels). Freescale Semiconductor ...
Page 161
... LOGIC EDG5 EDG1 PIN PT6 LOGIC EDG6 EDG2 PIN PT7 EDG7 LOGIC EDG3 Figure 13-1. Timer Block Diagram in Latch Mode Freescale Semiconductor 16-BIT FREE-RUNNING 16 BIT MAIN TIMER MAIN TIMER M CLOCK COMPARATOR TC0 CAPTURE/COMPARE DELAY REGISTER COUNTER EDG0 TC0H HOLD REGISTER COMPARATOR ...
Page 162
... PAC0 PA0H HOLD REGISTER 0 RESET PAC1 PA1H HOLD REGISTER 0 RESET PAC2 PA2H HOLD REGISTER 0 RESET PAC3 PA3H HOLD REGISTER LATQ, BUFEN (QUEUE MODE) READ TC3H HOLD REGISTER READ TC2H HOLD REGISTER READ TC1H HOLD REGISTER READ TC0H HOLD REGISTER Freescale Semiconductor ...
Page 163
... When a pin is assigned to output an on-chip peripheral function, writing to this PORTT bit does not affect the pin. The data is stored in an internal latch such that if the pin becomes available for general-purpose output, the driven level will be the last value written to the PORTT bit. Freescale Semiconductor M68HC12B Family Data Sheet, Rev. 9.1 Timer Registers Figure 13-4 ...
Page 164
... EDG2 DELAY COUNTER EDG3 DELAY COUNTER M68HC12B Family Data Sheet, Rev. 9.1 0 8-BIT PAC0 (PACN0) PA0H HOLDING REGISTER INTERRUPT 0 8-BIT PAC1 (PACN1) PA1H HOLDING REGISTER 0 8-BIT PAC2 (PACN2) PA2H HOLDING REGISTER INTERRUPT 0 0 8-BIT PAC3 (PACN3) PA3H HOLDING REGISTER Freescale Semiconductor ...
Page 165
... CLK1 CLK0 PRESCALED CLOCK FROM TIMER INTERRUPT 8-BIT PAC3 (PACN3) INTERRUPT 8-BIT PAC1 (PACN1) Figure 13-4. 16-Bit Pulse Accumulators Block Diagram Freescale Semiconductor TIMCLK (TIMER CLOCK) 4:1 MUX CLOCK SELECT (PAMOD) 8-BIT PAC2 (PACN2) PACA 8-BIT PAC0 (PACN0) PACB M68HC12B Family Data Sheet, Rev. 9.1 ...
Page 166
... Figure 13-7. Output Compare 7 Mask Register (OC7M) Read: Anytime Write: Anytime 166 IOS6 IOS5 IOS4 IOS3 Select Register (TIOS FOC6 FOC5 FOC4 FOC3 OC7M6 OC7M5 OC7M4 OC7M3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 IOS2 IOS1 IOS0 Bit 0 FOC2 FOC1 FOC0 Bit 0 OC7M2 OC7M1 OC7M0 Freescale Semiconductor ...
Page 167
... OC7M, the corresponding data bit in OC7D is stored to the corresponding bit of the timer port. When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit. Freescale Semiconductor Figure 13-8. PULSE ACCUMULATOR A ...
Page 168
... Disables the main timer, including the counter; can be used for reducing power consumption 1 = Allows the timer to function normally 168 Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit TSWAI TSBCK TFFCA M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit Freescale Semiconductor ...
Page 169
... These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn compare (see becomes an output tied to OCn regardless of the state of the associated DDRT bit. To enable output action by OMn and OLn bits on the timer port, the corresponding bit in OC7M should be cleared. Freescale Semiconductor ...
Page 170
... EDG6B EDG6A EDG5B EDG3A EDG2B EDG2A EDG1B EDGnA Configuration 0 Capture disabled 1 Capture on rising edges only 0 Capture on falling edges only 1 Capture on any edge (rising or falling) M68HC12B Family Data Sheet, Rev. 9 Bit 0 EDG5A EDG4B EDG4A Bit 0 EDG1A EDG0B EDG0A Table 13-2. Freescale Semiconductor ...
Page 171
... Counter reset inhibited and counter runs free 1 = Counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is reset from $FFFF to $0000. Freescale Semiconductor C6I ...
Page 172
... Table 13-3. The newly selected prescale factor will not take effect until the Table 13-3. Prescaler Selection PR1 PR0 C6F C5F C4F C3F M68HC12B Family Data Sheet, Rev. 9.1 Prescale Factor 128 2 1 Bit 0 C2F C1F C0F Figure Freescale Semiconductor 13-19. ...
Page 173
... Timer Input Capture/Output Compare Registers Address: $0090–$0091 Bit 7 Read: Bit 15 Write: Reset: 0 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-21. Timer Input Capture/Output Compare Register 0 (TC0) Freescale Semiconductor 16-BIT MAIN TIMER DELAY COUNTER TCN INPUT CAPTURE REGISTER TCNH IC HOLDING REGISTER ...
Page 174
... Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 175
... Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to $0000. Freescale Semiconductor ...
Page 176
... E ÷ 64 clock is generated by the timer prescaler. 176 PAEN PAMOD PEDGE CLK1 Pin Action 0 Falling edge 1 Rising edge 0 Divide by 64 clock enabled with pin high level 1 Divide by 64 clock enabled with pin low level NOTE M68HC12B Family Data Sheet, Rev. 9 Bit 0 CLK0 PAOVI PAI Freescale Semiconductor ...
Page 177
... PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACN3 and PACN2 registers will clear all the flags in this register when TFFCA bit in register TSCR ($86) is set. Freescale Semiconductor Clock Source Use timer prescaler clock as timer counter clock ...
Page 178
... Write: Anytime 178 Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 179
... This bit is active only when the modulus down-counter is enabled (MCEN = 1). Writing a 1 into this bit loads the load register into the modulus counter count register. This also resets the modulus counter prescaler. Writing 0 to this bit has no effect. When MODMC = 0, the counter starts counting and stops at $0000. Reads of this bit will return always 0. Freescale Semiconductor ...
Page 180
... PORTx input The first input capture has been caused by a falling edge The first input capture has been caused by a rising edge. 180 Prescalar MCPR1 MCPR0 Division Rate POLF3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 POLF2 POLF1 POLF0 Freescale Semiconductor ...
Page 181
... After counting, the counter will be cleared automatically. Delay between two active edges of the input signal period should be longer than the selected counter delay. DLYx — Delay Counter Select Bits DLY1 Freescale Semiconductor ...
Page 182
... NOVW6 NOVW5 NOVW4 NOVW3 Channels). This will prevent the captured value to be overwritten until SH26 SH15 SH04 TFMOD M68HC12B Family Data Sheet, Rev. 9 Bit 0 NOVW2 NOVW1 NOVW0 Bit 0 PACMX BUFEN LATQ Freescale Semiconductor ...
Page 183
... The 8-bit pulse accumulators are cleared. 13.4.20 Timer Test Register Address: $00AD Bit 7 Read: 0 Write: Reset Unimplemented 1. Available only on MC68HC912B32 devices. Figure 13-41. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMOD = 1) Freescale Semiconductor Figure 13-19. In all other input capture cases, the 13.3.1.2 Buffered ...
Page 184
... Figure 13-43. Data Direction Register for Timer Port (DDRT) Read: Anytime Write: Anytime 184 PT6 PT5 PT4 PT3 I/OC6 I/OC5 I/OC4 I/OC3 NOTE DDT6 DDT5 DDT4 DDT3 M68HC12B Family Data Sheet, Rev. 9 Bit 0 PT2 PT1 PT0 I/OC2 I/OC1 I/OC0 Bit 0 DDT2 DDT1 DDT0 Freescale Semiconductor ...
Page 185
... PA0EN control bits in ICPACR ($A8) have no effect. PBOVI — Pulse Accumulator B Overflow Interrupt Enable Bit 0 = Interrupt inhibited 1 = Interrupt requested if PBOVF is set 13.4.24 Pulse Accumulator B Flag Register Address: $00B1 Bit 7 Read: 0 Write: Reset: 0 Figure 13-45. Pulse Accumulator B Flag Register (PBFLG) • Read:Anytime • Write:Anytime Freescale Semiconductor PBEN ...
Page 186
... Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit Bit 6 Bit 5 Bit 4 Bit 13.3.2 Pulse Accumulators). M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 187
... Timer Input Capture Holding Registers Address: $00B8 Bit 7 Read: Bit 15 Write: Reset: 0 Address: $00B9 Bit 7 Read: Bit 7 Write: Reset: 0 Figure 13-51. Timer Input Capture Holding Register 0 (TC0H) Freescale Semiconductor Bit 14 Bit 13 Bit 12 Bit ...
Page 188
... Bit 14 Bit 13 Bit 12 Bit Bit 6 Bit 5 Bit 4 Bit 13.3.1 IC Channels). M68HC12B Family Data Sheet, Rev. 9 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 189
... Sixteen-bit pulse accumulator B is active. PBEN = 0 Eight-bit pulse accumulators 1 and 0 can be enabled. See Control Register. Freescale Semiconductor Timer and Modulus Counter Operation in Different Modes 13.4.6 Timer System Control Register 13.4.16 Input Control Pulse Accumulators 13.4.16 Input Control Pulse Accumulators M68HC12B Family Data Sheet, Rev. 9.1 13 ...
Page 190
... Enhanced Capture Timer (ECT) Module 190 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 191
... I/O. The SPI subsystem, which is compatible with the M68HC11 SPI, includes new features such as SS output and bidirectional mode. SERIAL INTERFACE Figure 14-1. Serial Interface Block Diagram Freescale Semiconductor RxD SCI TxD I/O I/O ...
Page 192
... INT REQUEST LOGIC M68HC12B Family Data Sheet, Rev. 9.1 14-2. SCI TRANSMITTER LSB 10-11 BIT SHIFT REG TxD BUFFER/SC0DRL TxMTR CONTROL SC0CR2/SCI CTL 2 SCI RECEIVER LSB 10-11 BIT SHIFT REG RxD BUFFER/SC0DRL SC0SR1/INT STATUS SC0CR2/SCI CTL 2 Freescale Semiconductor TxD PS1 RxD PS0 ...
Page 193
... The clock source for the generator comes from the P clock. Desired SCI Baud Rate 110 300 600 1200 2400 4800 9600 14,400 19,200 38,400 Freescale Semiconductor Table 14-1. Baud Rate Generation BR Divisor for P = 4.0 MHz 2273 833 417 208 104 — ...
Page 194
... BTST — Reserved for test function BSPL — Reserved for test function BRLD — Reserved for test function 194 BSPL BRLD SBR12 SBR11 SBR6 SBR5 SBR4 SBR3 NOTE M68HC12B Family Data Sheet, Rev. 9 Bit 0 SBR10 SBR9 SBR8 Bit 0 SBR2 SBR1 SBR0 Freescale Semiconductor ...
Page 195
... DDS0/2) which is the single-wire case when using the SCI. WOMS bit still affects general-purpose output on TXD and RXD pins when SCIx is not using these pins Each pin operates in an open drain fashion if that pin is declared as an output. Freescale Semiconductor ...
Page 196
... If parity is enabled, this bit determines even or odd parity for both the receiver and the transmitter. An even number the data character causes the parity bit and an odd number of 1s causes the parity bit Even parity selected 1 = Odd parity selected 196 M68HC12B Family Data Sheet, Rev. 9.1 Freescale Semiconductor ...
Page 197
... As long as SBK remains set, the transmitter sends 0s. When SBK is changed to 0, the current frame of all 0s is finished before the TxD line goes to the idle state. If SBK is toggled on and off, the transmitter sends only 10 (or 11) 0s and then reverts to mark idle or sending data. Freescale Semiconductor 6 5 ...
Page 198
... RWU bit is set. Once cleared, IDLE is not set again until after RDRF has been set (after the line has been active and becomes idle again RxD line active 1 = RxD line idle 198 RDRF IDLE Unimplemented M68HC12B Family Data Sheet, Rev. 9 Bit Freescale Semiconductor ...
Page 199
... This bit is controlled by the receiver front end set during the RT1 time period of the start bit search cleared when an idle state is detected or when the receiver circuitry detects a false start bit (generally due to noise or baud rate mismatch Character is not being received Character is being received. Freescale Semiconductor ...
Page 200
... If a 9-bit format is used, the upper register should be written first to ensure that it is transferred to the transmitter shift register with the lower register. 200 Unimplemented U = Unaffected R6T6 R5T5 R4T4 R3T3 Unaffected by reset M68HC12B Family Data Sheet, Rev. 9 Bit Bit 0 R2T2 R1T1 R0T0 Freescale Semiconductor ...