71V2556S133PF IDT, Integrated Device Technology Inc, 71V2556S133PF Datasheet - Page 15

71V2556S133PF

Manufacturer Part Number
71V2556S133PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 71V2556S133PF

Density
4.5Mb
Access Time (max)
4.2ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
300mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
NOTE:
1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to V
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
3. For I/Os V
AC Test Loads
(Typical, ns)
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Symbol
Symbol
I
I
I
I
ΔtCD
SB1
SB2
SB3
DD
V
V
|I
|I
|I
LO
OL
OH
LI
LI
|
|
|
MAX,
Figure 2. Lumped Capacitive Load, Typical Derating
Operating Power
Supply Current
CMOS Standby
Power Supply Current
Clock Running Power
Supply Current
Idle Power
Supply Current
HD
6
5
4
3
2
1
inputs are cycling at the maximum frequency of read cycles of 1/t
= V
Input Leakage Current
LBO, JTAG and ZZ Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Parameter
DDQ
20 30 50
– 0.2V, V
I/O
LD
Capacitance (pF)
= 0.2V. For other inputs V
80
Device Selected, Outputs Open,
Device Deselected, Outputs
Open, V
< V
Device Deselected, Outputs
Open, V
< V
Device Selected, Outputs Open,
Parameter
ADV/LD = X, V
V
f = f
CEN > V
V
IN
IN
Figure 1. AC Test Load
LD
LD
100
> V
MAX
> V
, f = 0
,
IH
(2.3)
HD
DD
DD
Test Conditions
Z
IH
or < V
0
, V
or < V
= Max., V
= Max., V
(2,3)
= 50Ω
DD
DD
IL
= Max.,
LD
, f = f
= Max.,
, f = f
(1)
IN
IN
HD
50Ω
MAX
> V
> V
MAX
= V
V
4875 drw 05
DDQ
(2)
HD
HD
DD
(2,3)
200
4875 drw 04
DD
or
or
– 0.2V, V
/2
and ZZ will be internally pulled to V
I
I
V
V
V
OL
OH
DD
DD
OUT
6.42
Com'l Only
= +6mA, V
= -6mA, V
(1)
,
,
= Max., V
= Max., V
15
CYC
200MHz
= 0V to V
LD
400
130
AC Test Conditions
(V
(V
40
40
; f=0 means no input lines are changing.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
= 0.2V.
DDQ
DD
(V
DD
DD
IN
IN
DDQ
= 3.3V±5%)
Test Conditions
= 0V to V
= 0V to V
= Min.
DD
= Min.
= 2.5V)
Com'l
, Device Deselected
350
120
40
40
= 3.3V±5%)
166MHz
DD
DD
Commercial and Industrial Temperature Ranges
360
Ind
130
45
45
SS
if it is not actively driven in the application.
Com'l
300
110
40
40
133MHz
310
Ind
120
45
45
Min.
2.0
___
___
___
___
Com'l
250
100
40
40
100MHz
See Figure 1
0 to 2.5V
(V
(V
Max.
0.4
DDQ
DDQ
2ns
30
___
5
5
260
Ind
110
45
45
/2)
/2)
4875 tbl 22
4875 tbl 21
4875 tbl 23
Unit
µA
µA
µA
Unit
V
V
mA
mA
mA
mA

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