71V2556S133PF IDT, Integrated Device Technology Inc, 71V2556S133PF Datasheet - Page 16

• Manufacturer Part Number: 71V2556S133PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V2556S133PF

• Density: 4.5Mb
• Access Time (max): 4.2ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

AC Electrical Characteristics
(V
NOTES:
1. t
2. Measured as HIGH above 0.6V
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t
Output Parameters
Set Up Times
Hold Times
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
CYC
F
CH
CL
CD
CDC
CLZ
CHZ
OE
OLZ
OHZ
SE
SA
SD
SW
SADV
SC
SB
HE
HA
HD
HW
HADV
HC
HB
(1)
DD
Symbol
The specs as shown do not imply bus contention because t
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
(2)
(2)
F
(3,4,5)
(3,4)
(3,4,5)
(3,4)
= 1/t
= 3.3V±5%, Commercial and Industrial Temperature Ranges)
CYC
.
Clock Cycle Time
Clock Frequence
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Valid Data
Clo ck High to Data Change
Clo ck High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
Clock Enable Setup Time
Data In Setup Time
Read/Write (R/W) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup
Clock Enable Hold Time
Data In Hold Time
Read/Write (R/W) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
Address Setup Time
Advance/Load (ADV/LD) Setup
Time
Time
Address Hold Time
Advance/Load (ADV/LD) Hold Time
Parameter
DDQ
and LOW below 0.4V
Min.
____
1.8
1.8
____
____
____
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
0
1
1
1
DDQ
CLZ
200MHz
.
is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than t
CHZ
Max.
200
3.2
3.2
3.5
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
(device turn-off) is about 1ns faster than t
3
6.42
16
Min.
____
1.8
1.8
____
____
____
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
0
1
1
1
166MHz
Max.
166
3.5
3.5
3.5
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
3
Commercial and Industrial Temperature Ranges
Min.
7.5
____
2.2
2.2
____
____
____
1.7
1.7
1.7
1.7
1.7
1.7
1.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0
1
1
1
CLZ
133MHz
(device turn-on) at a given temperature and voltage.
Max.
133
4.2
4.2
4.2
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
3
Min.
____
3.2
3.2
____
____
____
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
0
1
1
1
100MHz
Max.
100
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
3
5
5
4875 tbl 24
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHZ
,