71V2556S133PF IDT, Integrated Device Technology Inc, 71V2556S133PF Datasheet - Page 2

71V2556S133PF

Manufacturer Part Number
71V2556S133PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 71V2556S133PF

Density
4.5Mb
Access Time (max)
4.2ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
300mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
I/O
BW
CE
I/O
ADV/LD
Symbol
A
TRST
V
CEN
P1
LBO
TMS
TDO
R/W
CLK
TCK
CE
V
V
0
1
OE
TDI
0
1
ZZ
DDQ
-A
, CE
-I/O
-BW
DD
SS
-I/O
2
17
31
P4
2
4
Linear Burst Order
Test Mode Select
Data Input/Output
Test Data Output
Advance / Load
Address Inputs
Test Data Input
Individual Byte
Power Supply
Power Supply
Write Enables
Output Enable
Pin Function
Clock Enable
Chip Enables
Read / Write
Chip Enable
Sleep Mode
JTAG Reset
Test Clock
(Optional)
Ground
Clock
(1)
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inp uts. The address register is triggered by a combination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sample d high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
device two cycles later. BW
Synchronous active low chip enable. CE
(CE
deselect cycle. The ZBT
after deselect is initiated.
Synchronous active high chip enable. CE
inverted polarity but otherwise identical to CE
made with respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO
is low the Linear burst sequence is selected. LBO is a static input and it must not change during
device operation.
I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write
cycles. In normal operation, OE can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
Serial input of registers placed betwe en TDI and TDO. Sampled on rising edge of TCK. This pin has
an internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
Serial output of registers placed betwee n TDI and TDO. This output is active depe nding on the state of
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
reset occurs automatically at power up and also resets using TMS and TCK p er IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V2556/2558 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
Ground.
ADV/LD is a synchronous input that is used to load the internal reg isters with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
when ADV/LD is sampled high.
Write access to the memory array. The data bus activity for the current cycle takes place two clock
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
This is the clock input to the IDT71V2556/58. Except for OE, all timing references for the device are
Asynchronous output enable. OE must be low to read data from the 71V2556/58. When OE is high the
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
the TAP controller.
This pin has an internal pulldown
3.3V core power supply.
2.5V I/O Supply.
1
or CE
2
sampled high or CE
6.42
2
TM
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles
1
-BW
4
2
can all be tied low if always doing write to the entire 36-bit word.
sampled low) and ADV/LD low at the rising edg e of clock, initiates a
1
2
and CE
Commercial and Industrial Temperature Ranges
is used with CE
1
Description
and CE
2
are used with CE
2
.
1
and CE
2
2
to enable the chip. CE
to enable the IDT71V2556/58.
2
1
-BW
has
4875 tbl 02
4
)

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