HDMP-1032 Avago Technologies US Inc., HDMP-1032 Datasheet - Page 20

• Manufacturer Part Number: HDMP-1032
• Manufacturer: Avago Technologies US Inc.

Specifications of HDMP-1032

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 150C
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

HDMP-1034 (Rx) Pin Definition (continued)
Pass System
RXDSLIP
SHFIN
SHFOUT
SRQIN
SRQOUT
Test Mode/No Connect Pins
TSTCLK
#RESET
WSYNCDSB
NC
20
13
14
34
15
12
35
36
21
27
6
O-TTL
O-TTL
O-TTL
I-TTL
I-TTL
I-TTL
I-TTL
I-TTL
Rx Word Slip: This output is asserted whenever the phase of the
parallel word relative to the reference clock has exceeded the
range of the internal delay, which results in a slippage of one
word. See discussion of PASS system on page 7.
Shift Input: This input controls the delay of the parallel bits to
be clocked out by REFCLK when PASSENB=1. In a single Rx
configuration, SHFIN is connected to SHFOUT. In a multiple Rx
configuration, all SHFIN are connected to the master’s SHFOUT.
Shift Output: This output, normally connected to SHFIN, is
generated based on the relative phase between REFCLK and
the internal parallel output bits.
Shift Request Input: In a daisy chain configuration, this input
allows a shift request to be propagated to the master. SRQIN is
connected to the SRQOUT of the previous Rx in a multi-receiver
configuration.
Shift Request Output: In a daisy chain configuration, this output
is connected to the SRQIN input of the next receiver. SRQOUT
goes high when a SRQIN=1 or when the relative phase between
the REFCLK and the internal parallel bits requires a shift.
External Serial Rate Clock Input: When RXDIV1/0 = 1/1, this input
is used in place of the normal VCO signal, effectively disabling
the PLL and allowing the user to provide an external serial clock
for testing. Pin is normally tied to V
Reset: When this active low input is asserted the word alignment
is reset. Upon release (low to high) the normal word alignment
process is reinstated. Pin used for test purposes and is normally
tied to V
Word Sync Disable: When high, disables resynchronization to
word edge upon errors encountered in the C-field of the incoming
encoded word. Pin used for test purposes and is normally tied low.
No Connect: These pins should be left unconnected.
CC
_TTL.
CC
_TTL.