HDMP-1032 Avago Technologies US Inc., HDMP-1032 Datasheet - Page 22

HDMP-1032

Manufacturer Part Number
HDMP-1032
Description
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HDMP-1032

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 150C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant

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Appendix: Internal Architecture Information
Line Code Description
The HDMP-1032/1034 line code
is Conditional Invert Master Tran-
sition (CIMT) as illustrated in
Figure 9. The CIMT line code
uses three types of words: Data
words, Control words, and Idle
words. Idle words are generated
internally by the Tx when both
TXDATA and TXCNTL are low.
Each word consists of a Word
Field (W-Field) followed by a
Coding Field (C-Field). The
C-Field has a master transition.
Users can send arbitrary informa-
tion carried by Data or Control
Words. The DC balance of the
line code is enforced automati-
cally by the Tx. Idle words have
a single rising edge at the master
transition when operating in
non-enhanced simplex mode.
The coding definitions are sum-
marized in the table on the next
Figure 9. HDMP-1032/1034 (Tx/Rx Pair) Line Code.
22
SERIAL
BIT
STREAM
IDLE
WORD
16 BITS
WORD
FIELD
WORD K
page. Note that the leftmost bit in
each table is the first bit to be
transmitted in time, while the
rightmost bit is the last bit to
be transmitted.
Data Word Codes
In Data Word mode, all 16 bits
of the Tx are transmitted to
the Rx, along with a flag bit. If
TXFLGENB=1, then the user
controls this bit with TXFLAG;
otherwise it is internally set to
alternate.
Control Word Codes
In Control Word mode, 14 bits are
transmitted to the Rx. The lower
7 bits X0-X6 are sent in the
w0-w6 space, and the upper
7 bits X7-X13 are sent in the
w9-w15 space. Bits w7 and w8
are forced 01 for true, and 10
for inverted control words. The
shifting of the word field is for
TRANSITION
CODING
MASTER
4 BITS
FIELD
WORD K+1
TRANSITION
MASTER
backward compatibility with pre-
vious versions of G-Links chip sets.
Idle Word and Error Codes
Two Idle Words, IW1a and IW1b
are provided. Unused word codes
are mapped into Error States.
Enhanced Simplex Mode
In this mode (ESMPXENB=1),
the flag bit is scrambled at the
Tx and descrambled at the Rx.
Since the Rx uses the scrambled
flag bit for frame alignment, it is
also defined for Control and Idle
Words. However, the flag bit is
only available to the user in the
Data Word mode. The first bit
w0 is also scrambled to aid word
alignment.

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