HDMP-1032 Avago Technologies US Inc., HDMP-1032 Datasheet - Page 9

HDMP-1032

Manufacturer Part Number
HDMP-1032
Description
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HDMP-1032

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Operating Temp Range
0C to 150C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant

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Multiple Channel Configuration
The connections for a multiple
channel configuration are shown
in Figure 4.3. The daisy-chain
signals SRQIN and SRQOUT are
used to allow each receiver’s PASS
system shift requests to propagate
to the master, which is the last of
the chain. The master then con-
trols the shift command SHFOUT,
which is tied common to the
SHFIN of each receiver. The first
9
Figure 4.3. Multiple channel configuration with PASS Enabled (PASSENB=1).
DATA 16 BITS
DATA 16 BITS
DATA 16 BITS
TX[0-15]
TXCLK
TX[0-15]
TXCLK
TX[0-15]
TXCLK
Tx
Tx
Tx
SRQIN in the chain is grounded;
the SRQOUT of the master as
well as the SHFOUT outputs of
the slave units are left uncon-
nected.
When the internal parallel data
boundary of the master, or any
of the slaves come within 10% of
the REFCLK, the RXDSLIP output
is set high by the respective Rx,
HSOUT–
HSOUT–
HSOUT–
+V
+V
+V
HSIN–
HSIN–
HSIN–
CC
CC
CC
PASSENB
SRQOUT
PASSENB
SRQOUT
PASSENB
SRQOUT
(MASTER)
SRQIN
SRQIN
SRQIN
(SLAVE)
(SLAVE)
NC
Rx
Rx
Rx
RXCLK0/1
RXCLK0/1
RXCLK0/1
SHFOUT
SHFOUT
SHFOUT
RX[0-15]
RX[0-15]
RX[0-15]
REFCLK
REFCLK
REFCLK
SHFIN
SHFIN
SHFIN
NC
NC
a shift request (SRQOUT=1) is
issued which propagates to the
master. The master again selects
an optimum SHFOUT, which sets
the DELAY blocks of all receivers
consistently.
The phase absorption margin for
a multiple channel configuration
is the same as the single channel
case, less the channel-to-channel
skews.
REFCLK

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