71V3558S133PF

Manufacturer Part Number71V3558S133PF
ManufacturerIDT, Integrated Device Technology Inc
71V3558S133PF datasheet
 


Specifications of 71V3558S133PF

Density4.5MbAccess Time (max)4.2ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)133MHzOperating Supply Voltage (typ)3.3V
Address Bus18bPackage TypeTQFP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current300mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count100
Word Size18bNumber Of Words256K
Lead Free Status / Rohs StatusNot Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Page 2/26

Download datasheet (478Kb)Embed
PrevNext
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Symbol
Pin Function
I/O
A
-A
Address Inputs
I
0
17
ADV/LD
Advance / Load
I
R/W
Read / Write
I
CEN
Clock Enable
I
BW
Individual Byte
I
-BW
1
4
Write Enables
CE
, CE
Chip Enables
I
1
2
CE
Chip Enable
I
2
CLK
Clock
I
I/O
-I/O
Data Input/Output
I/O
0
31
I/O
-I/O
P1
P4
LBO
Linear Burst Order
I
OE
Output Enable
I
V
Power Supply
N/A
DD
V
Power Supply
N/A
DDQ
V
Ground
N/A
SS
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Commercial and Industrial Temperature Ranges
Active
N/A
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
LOW
inputs, including clock are ignored and outputs re main unchanged. The effect of CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW
-BW
) must be valid. The byte write signal must also be valid on each cycle of
1
4
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW
always doing write to the entire 36-bit word.
Synchronous active low chip enable. CE
LOW
or CE
IDT71V3556/58. (CE
sampled high or CE
1
2
rising edge of clock, initiates a deselect cycle. The ZBT
the data bus will tri-state two clock cycles after deselect is initiated.
HIGH
Synchronous active high chip enable. CE
has inverted polarity but otherwise identical to CE
CE
2
This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the
N/A
device are made with respect to the rising edge of CLK.
N/A
Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
LOW
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE
LOW
is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In normal operation, OE can be tied low.
N/A
3.3V core power supply.
N/A
3.3V I/O Supply.
N/A
Ground.
6.42
2
Description
-BW
can all be tied low if
1
4
and CE
are used with CE
to enable the
1
2
2
sampled low) and ADV/LD low at the
2
TM
has a two cycle deselect, i.e.,
is used with CE
and CE
to enable the chip.
2
1
2
and CE
.
1
2
5281 tbl 02