71V3556S133PF IDT, Integrated Device Technology Inc, 71V3556S133PF Datasheet - Page 2

• Manufacturer Part Number: 71V3556S133PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V3556S133PF

• Density: 4.5Mb
• Access Time (max): 4.2ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
I/O
BW
CE
I/O
ADV/LD
Symbol
A
V
CEN
P1
LBO
R/W
CLK
CE
V
V
0
1
0
OE
1
DDQ
-A
, CE
-I/O
-BW
DD
SS
-I/O
2
17
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
31
P4
4
2
Linear Burst Order
Data Input/Output
Advance / Load
Address Inputs
Individual Byte
Write Enables
Output Enable
Power Supply
Power Supply
Pin Function
Clock Enable
Chip Enables
Read / Write
Chip Enable
Ground
Clock
N/A
N/A
N/A
I/O
I/O
I
I
I
I
I
I
I
I
I
I
Active
HIGH
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW
always doing write to the entire 36-bit word.
Synchronous active low chip enable. CE
IDT71V3556/58. (CE
rising edge of clock, initiates a deselect cycle. The ZBT
the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
CE
This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE
is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In normal operation, OE can be tied low.
3.3V core power supply.
3.3V I/O Supply.
Ground.
2
has inverted polarity but otherwise identical to CE
1
-BW
6.42
2
4
) must be valid. The byte write signal must also be valid on each cycle of
1
or CE
2
sampled high or CE
Commercial and Industrial Temperature Ranges
Description
1
2
and CE
is used with CE
2
2
sampled low) and ADV/LD low at the
are used with CE
1
and CE
TM
has a two cycle deselect, i.e.,
1
and CE
1
-BW
2
.
4
2
2
can all be tied low if
to enable the chip.
to enable the
5281 tbl 02