MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 120

• Manufacturer Part Number: MC68HC711K4CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711K4CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 24KB
• Total Internal Ram Size: 768Byte
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Resets and Interrupts
5.5.1 Non-Maskable Interrupts
5.5.1.1 Non-Maskable Interrupt Request (XIRQ)
5.5.1.2 Illegal Opcode Trap
Technical Data
120
Non-maskable interrupts can interrupt CPU operations at any time. The
most common use for such an interrupt is for serious system problems,
such as program runaway or power failure. The three sources of
non-maskable interrupt are:
The XIRQ input is an updated version of the non-maskable NMI input of
earlier MCUs. Upon reset, both the X bit and I bit of the CCR are set to
inhibit all maskable interrupts and XIRQ. After minimum system
initialization, software can clear the X bit by a transfer from accumulator
A to condition code register (TAP) instruction, enabling XIRQ interrupts.
Thereafter, software cannot set the X bit and the XIRQ interrupt
becomes non-maskable.
I bit-related interrupts do not affect the X bit, which has a higher priority
than they do in the interrupt priority logic. When an I bit-related interrupt
occurs, the CPU sets the I bit after stacking the CCR byte, but the X bit
remains unaffected. When an X bit-related interrupt occurs, the CPU
sets both the X and I bits after stacking the CCR. The RTI instruction
restores the X and I bits to their pre-interrupt request state when it pulls
the CCR from the stack.
The MCU includes an illegal opcode detection circuit to avoid attempting
to process undefined opcodes or opcode sequences. This mechanism
works for all unimplemented opcodes on all four opcode map pages.
When the circuit detects an illegal opcode, it generates an interrupt. The
CPU responds by pushing the current value of the program counter,
which is actually the address of the first byte of the illegal opcode, on the
stack. The illegal opcode service routine can use this stacked address
as a pointer to the illegal opcode to correct it. To avoid repeated
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Freescale Semiconductor, Inc.
For More Information On This Product,
XIRQ pin
Illegal opcode trap
Software interrupt instruction (SWI)
Go to: www.freescale.com
Resets and Interrupts
M68HC11K Family
MOTOROLA