MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 123

• Manufacturer Part Number: MC68HC711K4CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711K4CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 24KB
• Total Internal Ram Size: 768Byte
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

5.7 Reset and Interrupt Processing
M68HC11K Family
MOTOROLA
NOTE:
Address: $003C
Any single maskable interrupt can be given priority over other maskable
interrupts by writing the appropriate value to the PSEL bits in the HPRIO
register (see
still subject to global masking by the I bit in the CCR or by any associated
local bits. Interrupt vectors are not affected by priority assignment.
To avoid race conditions, HPRIO is designed so that bits PSEL[4:0] can
be written only while the I-bit is set (interrupts are inhibited).
PSEL[4:0] — Priority Select Bits
This section presents flow diagrams of the reset and interrupt processes.
Figure 5-8
detection relates to normal opcode fetches.
of a block in
shows the resolution of interrupt sources within the SCI subsystem.
Reset:
Read:
Write:
These bits select one interrupt source to have the highest priority, as
explained in
Freescale Semiconductor, Inc.
For More Information On This Product,
RBOOT
Bit 7
0
illustrates how the CPU begins from a reset and how interrupt
Go to: www.freescale.com
Figure 5-7. Highest Priority I-Bit Interrupt
Figure 5-8
Figure
Resets and Interrupts
and Miscellaneous Register (HPRIO)
Table
SMOD
6
0
5-7). An interrupt that is assigned highest priority is
5-7.
and illustrates interrupt priorities.
MDA
5
0
PSEL4
4
0
PSEL3
3
0
Figure 5-9
Reset and Interrupt Processing
PSEL2
2
1
Resets and Interrupts
is an expansion
PSEL1
Figure 5-10
1
1
Technical Data
PSEL0
Bit 0
0
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