MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 234

• Manufacturer Part Number: MC68HC711K4CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711K4CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 24KB
• Total Internal Ram Size: 768Byte
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Memory Expansion and Chip Selects
11.3.2 Control Registers
11.3.2.1 Port G Assignment Register
Technical Data
234
NOTE:
NOTE:
window overlaps any portion of internal registers, RAM, or EEPROM,
that portion is repeated in all banks associated with that window. If a
window overlaps (EP)ROM, the (EP)ROM is present in all banks with
XA[18:16] = 0:0:0.
The reset vector most commonly resides in on-chip (EP)ROM at address
$FFFE–$FFFF. However, if the (EP)ROM is disabled or mapped at
address $2000–$7FFF, the reset vector is fetched from external memory
at $FFFE–$FFFF. When expanded memory is enabled, the reset vector
is fetched from external memory at $7FFE–$7FFF, regardless of the
presence of on-chip (EP)ROM.
Expansion address lines are enabled by the port G assignment register
(PGAR). The size and position of memory windows are controlled by the
memory mapping size (MMSIZ) and memory mapping window base
(MMWBR) registers, respectively. The memory mapping window control
registers, MM1CR and MM2CR, select the particular bank or page of
expanded memory present in the window(s) at a given time.
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
The port G assignment register (PGAR) sets each of port G pins 5:0 as
either an input/output (I/O) pin or memory expansion address line.
Clearing a bit configures the corresponding port G pin as GPIO; setting
the bit configures the pin as an expansion address line. If neither bank
uses a particular expansion address bit, the corresponding pin is
available for GPIO.
A special case exists for the address lines that overlap the CPU address
lines XA[15:13]. If these lines are selected as expansion address lines in
PGAR, but are not used in either window, the corresponding CPU
address line is still output on the appropriate pin.
Freescale Semiconductor, Inc.
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Memory Expansion and Chip Selects
Go to: www.freescale.com
M68HC11K Family
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