MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 47

MC68HC711K4CFN3

Manufacturer Part Number
MC68HC711K4CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC711K4CFN3

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
24KB
Total Internal Ram Size
768Byte
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

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3.3.1 Accumulators A, B, and D (ACCA, ACCB, and ACCD)
3.3.2 Index Register X (IX)
3.3.3 Index Register Y (IY)
M68HC11K Family
MOTOROLA
Accumulators A and B are general-purpose 8-bit registers that hold
operands and results of arithmetic calculations or data manipulations.
Some instructions treat these two accumulators as a single double-byte
(16-bit) accumulator called accumulator D. Most operations can use
either accumulator A or B, with these exceptions:
The IX register provides a 16-bit indexing value that can be added to the
8-bit offset provided in an instruction to create an effective address. The
IX register can be used also as a counter or as a temporary storage
register.
The IY register provides a 16-bit indexed mode function similar to that of
the IX register. Instructions using the IY register require an extra byte of
machine code and an extra cycle of execution time because of the way
the opcode map is implemented.
Freescale Semiconductor, Inc.
For More Information On This Product,
The ABX and ABY instructions add the contents of 8-bit
accumulator B to the contents of 16-bit register X or Y, but there
are no equivalent instructions that use A instead of B.
The TAP and TPA instructions transfer data from accumulator A
to the condition code register or from the condition code register
to accumulator A. However, there are no equivalent instructions
that use B rather than A.
The DAA instruction adjusts accumulator A after binary-coded
decimal (BCD) arithmetic operations, but there is no equivalent
BCD instruction to adjust accumulator B.
The add, subtract, and compare instructions associated with both
A and B (ABA, SBA, and CBA) only operate in one direction,
making planning ahead important to ensure the correct operand is
in the correct accumulator.
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
Technical Data
47

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