MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 52
MC68HC711K4CFN3
Manufacturer Part Number
MC68HC711K4CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711K4CFN3.pdf
(290 pages)
Specifications of MC68HC711K4CFN3
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
24KB
Total Internal Ram Size
768Byte
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711K4CFN3
Manufacturer:
MOLEX
Quantity:
12 000
Part Number:
MC68HC711K4CFN3
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Central Processor Unit (CPU)
3.3.6.7 Non-Maskable Interrupt (X)
3.3.6.8 Stop Disable (S)
3.4 Data Types
Technical Data
52
NOTE:
Setting the XIRQ mask (X) bit disables non-maskable interrupts from the
XIRQ pin. Every reset sets the X bit by default and only a software
instruction can clear it. When the processor recognizes a non-maskable
interrupt, it stacks the registers, sets the X and I bits, and then fetches
the interrupt vector. An interrupt service routine usually ends with a
return from interrupt (RTI), which restores the registers to the values that
were present before the interrupt occurred and clears the X bit. Only
hardware or an acknowledge can set the X bit. Only software can clear
the X bit (for example, the TAP instruction which transfers data from
accumulator A to the condition code register). There is no hardware
action for clearing X.
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the S bit is set,
the CPU treats a STOP instruction as if it were a no-operation (NOP)
instruction and continues to the next instruction.
S is set by reset and STOP is disabled by default.
The STOP instruction can be cleared by using the TAP instruction which
transfers data from accumulator A to the condition code register.
The MC68HC11 CPU supports these data types:
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
•
•
•
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Freescale Semiconductor, Inc.
For More Information On This Product,
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
Central Processor Unit (CPU)
Go to: www.freescale.com
M68HC11K Family
MOTOROLA
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