MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 107

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

5.3.1 Power-On Reset (POR)
5.3.2 External Reset (RESET)
5.3.3 Computer Operating Properly (COP) System
M68HC11K Family
MOTOROLA
NOTE:
A positive transition on V
power-up conditions. POR cannot be used to detect drops in power
supply voltages. The CPU delays 4064 internal clock cycles after the
oscillator becomes active to allow the clock generator to stabilize, then
checks the RESET pin. If RESET is at logical 0, the CPU remains in the
reset condition until the RESET pin goes to logical 1.
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic 1 in less than two
E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for four E-clock cycles, then released. Two E-clock cycles later, it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
It is not advisable to connect an external resistor capacitor (RC)
power-up delay circuit to the reset pin of M68HC11 devices because the
circuit charge time constant can cause the device to misinterpret the
type of reset that occurred.
The MCU includes a COP system to help protect against software
failures. When the COP is enabled, software periodically reinitializes a
free-running watchdog timer before it times out and resets the system.
Such a system reset indicates that a software error has occurred.
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Resets and Interrupts
DD
generates a POR, which is used only for
Resets and Interrupts
Sources of Resets
Technical Data
107