MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 171

MC68HC711KS2CFN3

Manufacturer Part Number
MC68HC711KS2CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC711KS2CFN3

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

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Price
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MC68HC711KS2CFN3
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Part Number:
MC68HC711KS2CFN3
Manufacturer:
FREESCA
Quantity:
3 184
8.4.4 Slave Select (SS)
8.4.5 SPI Timing
M68HC11K Family
MOTOROLA
(CPHA = 0) DATA OUT
(CPHA = 1) DATA OUT
FOR REFERENCE
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
SAMPLE INPUT
SS (TO SLAVE)
SCK CYCLE #
The slave select (SS) input is used to target specific devices in the SPI
system. It must be pulled low on a targeted slave device prior to any
communication with a master and must remain low for the duration of the
transaction. SS must always be high on any device in master mode.
Pulling SS low on a master mode device generates a mode fault error
(see
Four possible timing relationships are available through control bits
CPOL (clock polarity) and CPHA (clock phase) in the SPCR. These bits
must be the same in both master and slave devices. The master device
always places data on the MOSI line approximately a half-cycle before
the SCK clock edge. This enables the slave device to latch the data. See
Figure
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in
both master and slave devices.
MSB
Freescale Semiconductor, Inc.
Figure 8-2. Data Clock Timing Diagram
For More Information On This Product,
8.5.1 Mode Fault
MSB
1
8-2.
6
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
2
6
5
3
5
4
Error).
4
4
3
5
3
2
6
2
1
Serial Peripheral Interface (SPI)
7
1
LSB
SPI Signal Descriptions
LSB
8
Technical Data
171

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