MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 193

MC68HC711KS2CFN3

Manufacturer Part Number
MC68HC711KS2CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC711KS2CFN3

Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711KS2CFN3
Manufacturer:
NSC
Quantity:
1 001
Part Number:
MC68HC711KS2CFN3
Manufacturer:
FREESCA
Quantity:
3 184
9.5.2 Timer Input Capture 4/Output Compare 5 Register
M68HC11K Family
MOTOROLA
Address: $001E — TI4/O5 (High)
Address: $001F — TI4/O5 (Low)
TI4/05 functions as the input capture register for IC4 when PA3 is
configured for input capture 4.
When an edge on an input capture pin has been detected and
synchronized, the 16-bit free-running counter value is latched in the
associated input capture register pair in a single 16-bit parallel transfer.
The latch occurs on the opposite half-cycle of the phase two clock from
when the timer counter is incremented. This ensures a stable count
value whenever a capture occurs.
Input capture values can be retrieved from a TIC register with two
successive 8-bit reads. Reading the high-order byte inhibits a new
capture transfer for one bus cycle to ensure that the successive
low-order byte read corresponds with it. If a new input capture occurs
immediately after a high-order byte read, transfer is delayed for an
additional cycle, but the new value is not lost. To assure coherency
between the two bytes, use a double-byte read instruction such as LDD.
Reset:
Reset:
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 15
Bit 7
Bit 7
1
1
Go to: www.freescale.com
Figure 9-9. Timer Input Capture 4/Output
Bit 14
Bit 6
Timing System
6
1
1
Compare 5 Register (TI4/O5)
Bit 13
Bit 5
5
1
1
Bit 12
Bit 4
4
1
1
Bit 11
Bit 3
3
1
1
Bit 10
Bit 2
2
1
1
Input Capture (IC)
Bit 9
Bit 1
1
1
1
Timing System
Technical Data
Bit 0
Bit 8
Bit 0
1
1
193

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