MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 195

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

9.5.5 Timer Control 2 Register
M68HC11K Family
MOTOROLA
Address: $0021
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
EDGx[B:A] — Input Capture Edge Control Bits
Reset:
Read:
Write:
If I4/O5I is set when IC4 is enabled and the I4/O5F flag bit is set, a
hardware interrupt sequence is requested.
These bit pairs determine the edge polarities on the input capture pins
that trigger the corresponding input capture functions. Each of the
input capture functions can be independently configured to detect
rising edges only, falling edges only, any edge (rising or falling), or to
disable the input capture function. The input capture functions
operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count
cycle.
Each EDGx bit pair is cleared (IC function disabled) by reset and must
be encoded according to the values in
corresponding input capture edge detector circuit. IC4 functions only
if the I4/O5 bit in the PACTL register is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
EDG4B
Bit 7
EDGxB
0
Figure 9-12. Timer Control 2 Register (TCTL2)
0
0
1
1
Go to: www.freescale.com
EDG4A
Table 9-3. Input Capture Edge Selection
Timing System
6
0
EDG1B
5
0
EDGxA
0
1
0
1
EDG1A
4
0
EDG2B
Table 9-3
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
3
0
EDG2A
ICx Configuration
2
0
to configure the
Input Capture (IC)
EDG3B
1
0
Timing System
Technical Data
EDG3A
Bit 0
0
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