MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 226

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Analog-to-Digital (A/D) Converter
10.4 A/D Control/Status Registers
10.4.1 System Configuration Options Register
Technical Data
226
NOTE:
The registers involved in A/D operation include OPTION, ADCTL, and
the four result registers ADR[1:4].
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
Bit 7 in the system configuration options register (OPTION), ADPU,
enables the A/D converter system. Setting ADPU applies power to the
A/D circuitry, including the charge pump that drives the analog switches.
Clearing ADPU removes power from the A/D system.
The gates of analog switches in the multiplexer are driven by a charge
pump that develops between seven and eight volts. The high gate
voltage assures low source-to-drain impedance for the analog signals.
Both the charge pump and the comparator circuits require up to 100 s
to stabilize after setting the ADPU bit.
The CSEL bit (bit 6) determines whether the A/D converter uses the
system E clock or an internal RC oscillator for synchronization. It is
cleared out of reset, selecting the E clock. This is the preferred setting at
normal operating frequencies because all switching and comparator
operations are synchronized to the main MCU clocks. This allows the
comparator output to be sampled at relatively quiet portions of the MCU
clock cycles.
When the E clock frequency is less than 750 kHz, charge leakage in the
capacitor array can cause errors. In this case, set the CSEL bit to select
the internal oscillator, which usually runs at about 2 MHz. The additional
error introduced by the asynchronous oscillator is about ± 1/2 LSB (least
significant bit), which is usually less than that incurred by a slow clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
Analog-to-Digital (A/D) Converter
Go to: www.freescale.com
M68HC11K Family
MOTOROLA