MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 54

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Central Processor Unit (CPU)
3.6.1 Immediate
3.6.2 Direct
3.6.3 Extended
3.6.4 Indexed
Technical Data
54
In the immediate addressing mode, the byte(s) immediately following the
opcode contain the arguments. The number of bytes following the
opcode matches the size of the register or memory location being used.
Immediate instructions can be two, three, or (if a prebyte is required) four
bytes.
In the direct addressing mode, the user specifies only the low-order byte
of the effective address in a single byte following the opcode. The
processor assumes the high-order byte of the address to be $00. Thus,
the CPU accesses addresses $00–$FF directly, using 2-byte
instructions. This reduces execution time by eliminating the additional
memory access required for the high-order address byte. Most
applications reserve this 256-byte area for frequently referenced data,
but various combinations of internal registers, RAM, or external memory
can occupy these addresses.
In the extended addressing mode, the two bytes following the opcode
byte contain the effective address of the argument. For this reason,
instructions are three bytes, or they are four bytes if a prebyte is
required.
In the indexed addressing mode, the CPU computes the effective
address of the argument by adding an 8-bit unsigned offset to the value
contained in an index register (IX or IY). Any memory location in the
64-Kbyte address space can be accessed with this mode. The
instructions are from two to five bytes.
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processor Unit (CPU)
Go to: www.freescale.com
M68HC11K Family
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