MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 57

MC68HC711KS2CFN3

Manufacturer Part Number

MC68HC711KS2CFN3

Description

Manufacturer

Freescale Semiconductor

Datasheet

1.MC68HC711KS2CFN3.pdf (290 pages)

Specifications of MC68HC711KS2CFN3

Cpu Family

HC11

Device Core Size

8b

Frequency (max)

4MHz

Interface Type

SCI/SPI

Program Memory Type

ROM

Program Memory Size

32KB

Total Internal Ram Size

1KB

# I/os (max)

51

Number Of Timers - General Purpose

8

Operating Supply Voltage (typ)

5V

Operating Supply Voltage (max)

5.5V

Operating Supply Voltage (min)

4.5V

On-chip Adc

8-chx8-bit

Instruction Set Architecture

CISC

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

68

Package Type

PLCC

Lead Free Status / Rohs Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

MC68HC711KS2CFN3

Manufacturer:

NSC

Quantity:

1 001

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

MC68HC711KS2CFN3

Manufacturer:

FREESCA

Quantity:

3 184

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M68HC11K Family

MOTOROLA

BRCLR(opr)

BRSET(opr)

BSET (opr)

CMPA (opr)

CMPB (opr)

Mnemonic

BITA (opr)

BITB (opr)

CLR (opr)

BEQ (rel)

BGE (rel)

BGT (rel)

BHS (rel)

BNE (rel)

BRA (rel)

BRN (rel)

BSR (rel)

BVC (rel)

BLO (rel)

BVS (rel)

BLE (rel)

BLS (rel)

BLT (rel)

BMI (rel)

BPL (rel)

BHI (rel)

CLRA

CLRB

CBA

CLC

CLV

CLI

(msk)

(rel)

(msk)

(rel)

(msk)

Branch if = Zero

Branch if

Branch if > Zero

Higher or Same

Branch if

Branch if Lower

Branch if Lower

Branch if < Zero

Compare A to B

Branch if Minus

Branch Always

Overflow Clear

Clear Overflow

Branch if not =

Branch if Bit(s)

Clear Carry Bit

Clear Interrupt

Accumulator A

Accumulator B

Branch if Plus

Clear Memory

Compare A to

Compare B to

Branch Never

Overflow Set

Bit(s) Test A

with Memory

Bit(s) Test B

with Memory

Subroutine

Operation

Bit(s) Clear

Branch to

Set Bit(s)

Branch if

Branch if

Branch if

Branch if

Branch if

or Same

Memory

Memory

Higher

Mask

Clear

Clear

Zero

Byte

Flag

Set

Zero

Zero

? Z + (N

? Z + (N

See

? (M) • mm = 0

? M • mm = 0

M + mm

Description

? N

? N

? C + Z = 0

? C + Z = 1

? C = 0

? C = 1

? N = 1

? N = 0

? Z = 1

? Z = 0

? V = 0

? V = 1

? 1 = 1

? 1 = 0

0

0

0

0

0

Figure 3-2

A – M

B – M

A – B

A • M

B • M

0

Table 3-1. Instruction Set (Sheet 2 of 7)

Freescale Semiconductor, Inc.

V = 0

V = 1

C

M

A

B

V

I

V) = 0

V) = 1

For More Information On This Product,

M

A

A

A

A

A

B

B

B

B

B

A

B

A

A

A

A

A

B

B

B

B

B

Central Processor Unit (CPU)

Addressing

Go to: www.freescale.com

Mode

REL

REL

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IMM

DIR

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18

18

18

18

18

18

18

18

Opcode

27

2C

2E

22

24

85

95

A5

A5

C5

D5

E5

E5

2F

25

23

2D

2B

26

2A

20

13

1F

1F

21

12

1E

1E

14

1C

1C

8D

28

29

11

0C

0E

7F

6F

6F

4F

5F

0A

81

91

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C1

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B5

F5

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Instruction

rr

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dd mm rr

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Operand

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Cycles

3

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2

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4

5

2

3

4

4

5

3

3

3

3

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6

7

8

6

7

8

6

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6

3

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2

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6

6

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2

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Central Processor Unit (CPU)

—

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Condition Codes

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Technical Data

Instruction Set

—

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1

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V

0

0

0

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0

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C

0

0

0

0

57

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