MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 62

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Central Processor Unit (CPU)
Technical Data
62
Mnemonic
TST (opr)
XGDX
XGDY
TSTA
TSTB
TPA
TSX
TSY
TXS
TYS
WAI
Cycle
*
**
Operands
dd
ff
hh
ii
jj
kk
ll
mm
rr
Operators
( )
•
+
:
–
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
= High-order byte of 16-bit extended address
= One byte of immediate data
= High-order byte of 16-bit immediate data
= Low-order byte of 16-bit immediate data
= Low-order byte of 16-bit extended address
= 8-bit mask (set bits to be affected)
= Signed relative offset $80 (–128) to $7F (+127)
Contents of register shown inside parentheses
Is transferred to
Is pulled from stack
Is pushed onto stack
Boolean AND
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction symbol or negation symbol (two’s complement)
Test for Zero or
Test A for Zero
Test B for Zero
Transfer Stack
Transfer Stack
Stack Pointer
Stack Pointer
Register to A
Transfer X to
Transfer Y to
Transfer CC
Exchange D
Exchange D
Pointer to X
Pointer to Y
Operation
or Minus
or Minus
Interrupt
(offset relative to address following machine code offset byte))
Wait for
Minus
with X
with Y
Stack Regs & WAIT
IX
IY
Description
SP + 1
SP + 1
IX – 1
IY – 1
CCR
M – 0
A – 0
B – 0
D, D
D, D
Table 3-1. Instruction Set (Sheet 7 of 7)
Freescale Semiconductor, Inc.
SP
SP
For More Information On This Product,
A
IX
IY
IX
IY
A
B
Central Processor Unit (CPU)
Addressing
Go to: www.freescale.com
Mode
INH
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
INH
INH
INH
18
18
18
18
Opcode
07
7D
6D
6D
4D
5D
30
30
35
35
3E
8F
8F
Instruction
hh ll
ff
ff
Operand
—
—
—
—
—
—
—
—
—
—
Condition Codes
—
0
1
Cycles
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
**
2
6
6
7
2
2
3
4
3
4
3
4
—
—
—
—
—
—
—
—
—
—
—
S
—
—
—
—
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
—
—
—
H
Condition Codes
—
—
—
—
—
—
—
—
—
—
—
I
M68HC11K Family
—
—
—
—
—
—
—
—
N
MOTOROLA
—
—
—
—
—
—
—
—
Z
—
—
—
—
—
—
—
—
V
0
0
0
—
—
—
—
—
—
—
—
C
0
0
0