MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 71

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

M68HC11K Family
MOTOROLA
1. Can only be written once in first 64 cycles out of reset in normal modes
2. Not available on M68HC11KS devices
$003C
$003D
$003A
$003B
$003E
$003F
$0040
$0055
$0056
$0057
Addr.
to
EEPROM Programming
Window Base Register
Arm/Reset COP Timer
Memory Mapping Size
RAM and I/O Mapping
System Configuration
See pages 88, 101,
See pages 235, 243
Register (MMSIZ)
Highest Priority I-Bit
Register (CONFIG)
See pages 80, 123
Interrupt and Misc.
Register (HPRIO)
Circuitry Register
Memory Mapping
Register (INIT)
Control Register
Register Name
Test 1 Register
See page 110.
See page 236.
Figure 4-1. Register and Control Bit Assignments (Sheet 7 of 11)
See page 91.
See page 84.
(MMWBR)
(COPRST)
(PPROG)
Reserved
Reserved
108, 147
(TEST1)
(1)
(2)
(2)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
ROMAD
RBOOT
MXGS2
W2A15
RAM3
TILOP
Operating Modes and On-Chip Memory
Bit 7
ODD
Bit 7
—
—
R
R
0
0
0
0
0
0
Go to: www.freescale.com
= Unimplemented
MXGS1
W2A14
SMOD
EVEN
RAM2
Bit 6
—
R
R
6
0
0
0
0
0
1
1
0
0
W2SZ1
W2A13
OCCR
RAM1
CLKX
MDA
Bit 5
LVPI
—
—
R
R
5
0
0
0
0
0
0
PAREN
W2SZ0
PSEL4
RAM0
CBYP
BYTE
Bit 4
—
4
0
0
0
0
0
R
R
0
0
0
R
Operating Modes and On-Chip Memory
= Reserved
NOSEC
W1A15
PSEL3
REG3
ROW
DISR
Bit 3
R
R
3
0
0
0
0
0
1
0
0
0
NOCOP
ERASE
W1A14
PSEL2
REG2
FCM
Bit 2
—
R
R
2
0
0
1
0
0
0
0
0
U = Undefined
ROMON
W1SZ1
W1A13
EELAT
PSEL1
Control Registers
FCOP
REG1
Bit 1
—
R
R
1
0
0
1
0
0
0
0
Technical Data
EEPGM
W1SZ0
PSEL0
REG0
EEON
Bit 0
Bit 0
—
R
R
0
0
0
0
0
0
0
0
0
71