FAN5234QSCX_NL Fairchild Semiconductor, FAN5234QSCX_NL Datasheet - Page 10

• Manufacturer Part Number: FAN5234QSCX_NL
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5234QSCX_NL

• Dc To Dc Converter Type: Synchronous Buck Controller/PWM DC to DC Controller
• Number Of Outputs: 1
• Pin Count: 16
• Input Voltage: 5 to 24V
• Output Voltage: 0.9 to 5.5V
• Package Type: QSOP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Operating Temperature (min): -10C
• Operating Temperature (max): 85C
• Lead Free Status / Rohs Status: Compliant

PRODUCT SPECIFICATION
Setting the Output Voltage
The internal reference is 0.9V. The output is divided down by
a voltage divider to the VSEN pin (for example, R1 and R2
in Figure 1). The output voltage therefore is:
To minimize noise pickup on this node, keep the resistor to
GND (R2) below 2K. We selected R2 at 1.82K. Then choose
R5:
Output Inductor Selection
The minimum practical output inductor value is the one that
keeps inductor current just on the boundary of continuous
conduction at some minimum load. The industry standard
practice is to choose the ripple current to be somewhere from
15% to 35% of the nominal current. At light load, the ripple
current also determines the point where the converter will
automatically switch to hysteretic mode of operation (I
to sustain high efficiency. The following equations help to
choose the proper value of the output filter inductor.
where ∆I is the inductor ripple current, which we will choose
for 20% of the full load current and ∆V
output ripple voltage allowed.
for this example we'll use:
V
∆I = 20% * 3.5A = 0.7A
F
therefore
L ≈ 8µH
Output Capacitor Selection
The output capacitor serves two major functions in a switch-
ing power supply. Along with the inductor it filters the
sequence of pulses produced by the switcher, and it supplies
the load transient currents. The output capacitor require-
ments are usually dictated by ESR, Inductor ripple current
(∆I) and the allowable ripple voltage (∆V).
10
R5
SW
IN
=
= 20V, V
L
= 300KHz.
∆I
ESR
(
------------------------------------------------------- -
=
1.82K
0.9V
----------- -
R2
=
V
----------------------------- -
F
<
2 I
IN
SW
∆V
------- -
–
OUT
=
)
∆I
–
•
V
0.9
MIN
×
V
-------------------------------- -
(
1.8V 0.9
OUT
OUT
∆I
= 1.8V
=
R1
×
–
–
∆V
------------------
0.9V
V
--------------
ESR
V
OUT
OUT
IN
)
=
1.82K
OUT
is the maximum
(12)
MIN
(9a)
(9b)
(10)
(11)
)
For our example,
In addition, the capacitor's ESR must be low enough to allow
the converter to stay in regulation during a load step. The rip-
ple voltage due to ESR for the converter in Figure 1 is
100mV P-P. Some additional ripple will appear due to the
capacitance value itself:
which is only about 1.5mV for the converter in Figure 1 and
can be ignored.
The capacitor must also be rated to withstand the RMS cur-
rent which is approximately 0.3 X (∆I), or about 210mA for
our example. High frequency decoupling capacitors should
be placed as close to the loads as physically possible.
Input Capacitor Selection
The input capacitor should be selected by its ripple current
rating. The input RMS current at maximum load current (I
is:
where the converter duty cycle;
the circuit in Figure 1, with V
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (P
conduction (P
In typical applications, the FAN5234 converter's output volt-
age is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should be therefore be selected to min-
imize conduction losses, thereby selecting a MOSFET with
low R
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and it's conduction loss will therefore have less of
an impact. Q1, however, sees most of the switching losses,
so Q1's primary selection criteria should be gate charge.
High-Side Losses:
Figure 8 shows a MOSFET's switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing V
constant current charging the gate. The x-axis therefore is
also representative of gate charge (Q
and it controls t1, t2, and t4 timing. C
from the gate driver during t3 (as V
charge (Q
fied or can be derived from MOSFET datasheets.
I
RMS
DS(ON)
∆V
I
G
=
RMS
=
) parameters on the lower graph are either speci-
.
---------------------------------------- -
C
1.6A
COND
OUT
=
I
) losses.
ESR
×
L
∆I
8
D D
×
(
MAX
–
F
SW
2
)
IN
=
=6 calculates to:
∆V
------- -
∆I
D
DS
=
G
=
GD
) . C
V
--------------
is falling). The gate
GS
V
0.1V
----------- -
0.7A
OUT
receives the current
IN
REV. 1.0.10 5/3/04
vs. time with a
ISS
=
, which for
= C
142mΩ
GD
FAN5234
SW
+ C
(13)
) and
(14)
GS
L
)
,