AT28BV64B-25TI Atmel, AT28BV64B-25TI Datasheet - Page 3

• Manufacturer Part Number: AT28BV64B-25TI
• Manufacturer: Atmel

Specifications of AT28BV64B-25TI

• Density: 64Kb
• Interface Type: Parallel
• Organization: 8Kx8
• Access Time (max): 250ns
• Write Protection: Yes
• Data Retention: 10Year
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Supply Current: 15mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

3. Block Diagram
4. Device Operation
4.1
4.2
4.3
0299H–PEEPR–10/06
Read
Byte Write
Page Write
The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100 µs (t
t
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
BLC
limit is exceeded, the AT28BV64B will cease accepting data and commence the internal
WC
, a read operation will effectively be a polling operation.
BLC
) of the previous byte. If the
AT28BV64B
3