TC55V8512J-12

Manufacturer Part NumberTC55V8512J-12
ManufacturerToshiba
TC55V8512J-12 datasheet
 

Specifications of TC55V8512J-12

Density4MbAccess Time (max)12ns
Sync/asyncAsynchronousArchitectureNot Required
Clock Freq (max)Not RequiredMHzOperating Supply Voltage (typ)3.3V
Address Bus19bPackage TypeSOJ
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current170mAOperating Supply Voltage (min)3V
Operating Supply Voltage (max)3.6VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count36
Word Size8bNumber Of Words512K
Lead Free Status / Rohs StatusNot Compliant  
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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V8512J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high
density surface assembly.
FEATURES
Fast access time (the following are maximum values)
TC55V8512J/FT-12:12 ns
TC55V8512J/FT-15:15 ns
Low-power dissipation
(the following are maximum values)
Cycle Time
12
15
20
Operation (max)
170
140
130
Standby:4 mA (both devices)
PIN ASSIGNMENT
(TOP VIEW)
36 PIN SOJ
44 PIN TSOP
NC
NC
A17
A3
A17
1
36
NC
A2
A3
2
35
A4
A1
A2
3
34
A5
A0
A1
4
33
A6
CE
A0
5
32
A7
I/O1
6
31
I/O2
CE
OE
I/O1
7
30
I/O8
V
DD
I/O2
8
29
I/O7
GND
V
9
28
GND
I/O3
DD
GND
10
27
V
I/O4
DD
I/O3
11
26
I/O6
WE
I/O4
12
25
I/O5
A16
13
24
A8
A15
WE
A16
14
23
A9
A14
A15
15
22
A10
A13
A14
16
21
A11
A18
A13
17
20
A12
NC
A18
18
19
NU
NC
(TC55V8512J)
Single power supply voltage of 3.3 V ± 0.3 V
Fully static operation
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Package:
SOJ36-P-400-1.27 (J)
25
ns
TSOP II44-P-400-0.80 (FT)
110
mA
PIN NAMES
1
44
NC
2
43
NC
3
42
NC
4
41
A4
5
40
A5
6
39
A6
7
38
A7
8
37
OE
9
36
I/O8
10
35
I/O7
11
34
GND
12
33
V
DD
13
32
I/O6
14
31
I/O5
15
30
A8
16
29
A9
17
28
A10
18
27
A11
19
26
A12
20
25
NU
21
24
NC
22
23
NC
(TC55V8512FT)
TC55V8512J/FT-12,-15
(Weight: 1.35 g typ)
(Weight: 0.45 g typ)
A0 to A18
Address Inputs
I/O1 to I/O8
Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
V
Power (+3.3 V)
DD
GND
Ground
NC
No Connection
NU
Not Usable (Input)
2001-12-19 1/10

TC55V8512J-12 Summary of contents

  • Page 1

    ... OE ) provides fast memory access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. ...

  • Page 2

    ... COLUMN DECODER COLUMN ADDRESS BUFFER CLOCK A10 A11A13 CE RATING min (4 ns max) RC min (4 ns max 0° to 70°C) PARAMETER min (4 ns max) RC min (4 ns max) RC TC55V8512J/FT-12,- GND CE A18 VALUE −0.5 to 4.6 −0.5* to 4.6 −0. 0.5** DD 1.4 260 −65 to 150 − ...

  • Page 3

    ... Other Input = − 0.2 V, Other Input = V − TEST CONDITION = GND GND V I TC55V8512J/FT-12,-15 MIN TYP MAX −1  1 −1  1 −1  20 −1  1   2.4 − 0.2     0.4   0   t 170 cycle = 15 ns  ...

  • Page 4

    ... TC55V8512J/FT -12 -15 MAX MIN MAX   15      4   4   1   TC55V8512J/FT -12 -15 MAX MIN MAX   15   9   12   12   0   0   8   0   1  ...

  • Page 5

    ... Note 6) t OEE (See Note 6) t COE INDETERMINATE (See Note (See Note 6) t ODW (See Note 3) INDETERMINATE TC55V8512J/FT-12,- (See Note 6) t COD (See Note 6) t ODO VALID DATA OUT INDETERMINATE t WR (See Note 6) t OEW Hi-Z (See Note 4) INDETERMINATE VALID DATA IN ...

  • Page 6

    ... WRITE CYCLE CONTROLLED) Address Hi-Z OUT D IN (See Note (See Note 6) t ODW (See Note 6) t COE INDETERMINATE t DS VALID DATA IN TC55V8512J/FT-12,- Hi 2001-12-19 6/10 ...

  • Page 7

    ... Output Disable Time ・・・・・・・・・・・・・・・・ (A) 0.2 V VALID DATA OUT 0.2 V INDETERMINATE TC55V8512J/FT-12,-15 (B) 0.2 V Hi-Z 0.2 V INDETERMINATE 2001-12-19 7/10 ...

  • Page 8

    ... PACKAGE DIMENSIONS Weight: 1.35 g (typ) TC55V8512J/FT-12,-15 2001-12-19 8/10 ...

  • Page 9

    ... PACKAGE DIMENSIONS Weight: 0.45 g (typ) TC55V8512J/FT-12,-15 2001-12-19 9/10 ...

  • Page 10

    ... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TC55V8512J/FT-12,-15 000707EBA 2001-12-19 10/10 ...