ST52F513G3M6 STMicroelectronics, ST52F513G3M6 Datasheet

ST52F513G3M6

Manufacturer Part Number
ST52F513G3M6
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST52F513G3M6

Cpu Family
ST52
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Program Memory Type
Flash
Program Memory Size
8KB
Total Internal Ram Size
256Byte
# I/os (max)
22
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
SO
Lead Free Status / Rohs Status
Compliant

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Memories
Core
Clock and Power Supply
Interrupts
I/O Ports
July 2008
8 Kbytes Single Voltage Flash Memory
256 bytes of Register File
256 bytes of RAM
256 bytes Data EEPROM
In Situ Programming in Flash devices (ISP)
Single byte and Page modes and In Application
Programming for writing data in Flash memory
Readout protection and flexible write protection
Register File based architecture
107 basic instructions
Hardware multiplication and division
Decision Processor for the implementation of
Fuzzy Logic algorithms
Deep System and User Stacks
Up to 20 MHz clock frequency
Programmable Oscillator modes:
– 10 MHz internal oscillator
– External clock/ oscillator
Power-on reset (POR)
Programmable low-voltage detector (PLVD)
with 3 configurable thresholds
Power saving features
8 interrupt vectors with one SW Trap
Non-Maskable Interrupt (NMI)
Two Port Interrupts with up to 16 sources
From 10 up to 22 I/O PINs configurable in pull-
up, push-pull, weak pull-up, open-drain and
high-impedance
High current sink/source in all pins
®
ST52510xx
8-bit intelligent controller unit (ICU),
two timer/PWMs, ADC, I
Rev 17
Peripherals
Development tools
Table 1: Device summary
ST52510xx
ST52513xx
ST52510xx ST52513xx
Reference
On-chip 10-bit A/D Converter with 8 channel
analog multiplexer and Autocalibration.
2 Programmable 16 bit Timer/PWMs with
internal 16-bit Prescaler featuring:
– PWM output
– Input capture
– Output compare
– Pulse generator mode
Watchdog timer
Serial Communication Interface (SCI) with
asynchronous protocol (UART).
I
3-wire SPI Peripheral supporting Single
Master and Multi Master SPI modes
High level Software tools
‘C’ Compiler
In-Circuit Debugger
Low cost Programmer
Gang Programmer
2
C Peripheral with master and slave mode
ST52510F3, ST52510G3, ST52510Y3
ST52513F3, ST52513G3, ST52513Y3
LFBGA36
Part numbers
NOT FOR NEW DESIGN
2
C, SPI, SCI
1/136

Related parts for ST52F513G3M6

ST52F513G3M6 Summary of contents

Page 1

Memories 8 Kbytes Single Voltage Flash Memory ■ 256 bytes of Register File ■ 256 bytes of RAM ■ 256 bytes Data EEPROM ■ In Situ Programming in Flash devices (ISP) ■ Single byte and Page modes and In ...

Page 2

TABLE OF CONTENTS 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

ST52510xx ST52513xx 10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

ST52510xx ST52513xx 16.10 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

... Intelligent Controller Units (ICU), which can perform, both boolean and Fuzzy algorithms in an efficient manner, in order to reach the best performances that the two methodologies allow. Produced by STMicroelectronics using the reliable high performance CMOS process for Single Voltage Flash versions, ST52510/513 include integrated ...

Page 8

ST52510xx ST52513xx configuration registers, in order to avoid overlap with other data. Single Voltage Flash allows the user to reprogram the devices on-board by means of the In Situ Programming (ISP) feature possible to store in safe way ...

Page 9

Table 1.1 ST52510/513 Device Summary Device NVM ST52510Y3 8 K FLASH ST52510F3 8 K FLASH ST52510G3 8 K FLASH ST52513Y3 8 K FLASH ST52513F3 8 K FLASH ST52513G3 8 K FLASH COMMON FEATURES Watchdog Other Features Temperature Range Operating Supply ...

Page 10

ST52510xx ST52513xx Figure 1.1 ST52510/513 Block Diagram MEMORY FLASH ISP/IAP DATA RAM 256 bytes DATA EEPROM MEMORY INTERFACE CORE ALU & DECISION PROCESSOR CONTROL Register File 256 bytes PC POWER SUPPLY & PLVD VDD 10/136 DPU UNIT Input registers FLAGS ...

Page 11

Figure 1.2 ST52510/513 SO20 Pin Configuration PB0/VREF/AIN0 Figure 1.3 ST52510/513 SO16 Pin Configuration OscOut PB0/VREF/AIN0 PB1/AIN1 PA7/INT PA6/T0OUT Vdd 1 OscOut 2 SO20 OscIn 3 Vpp 4 5 PB1/AIN1 6 PB2/AIN2 7 PB3/AIN3 8 PB4/AIN4 9 PB5/AIN5 10 Vdd 1 ...

Page 12

ST52510xx ST52513xx Figure 1.4 ST52510/513 SDIP32/DIP28 Pin Configuration Vdd 1 VddIO 2 SDIP32 OscOut 3 OscIn 4 Vpp 5 PB0/VREF/AIN0 6 PB1/AIN1 7 PB2/AIN2 8 PB3/AIN3 9 PB4/AIN4 10 PB5/AIN5 11 PB6/AIN6 12 PB7AIN7 13 PC0/SCK 14 PC1/MOSI 15 N.C. ...

Page 13

See Section Output Driving Current Table 1.2 ST52510/513 SDIP32 Pin List SDIP32 NAME Class 1 Vdd 2 VddIO 3 OSCOUT 4 OSCIN 5 Vpp 6 PB0/VREF/AIN0 A 7 PB1/AIN1 A 8 PB2/AIN2 A 9 PB3/AIN3 A 10 PB4/AIN4 A 11 ...

Page 14

ST52510xx ST52513xx Table 1.3 ST52510/513 SO28 Pin List SO28 NAME Class 1 Vdd 2 OSCOUT 3 OSCIN 4 Vpp 5 PB0/VREF/AIN0 A 6 PB1/AIN1 A 7 PB2/AIN2 A 8 PB3/AIN3 A 9 PB4/AIN4 A 10 PB5/AIN5 A 11 PB6/AIN6 B ...

Page 15

Table 1.4 ST52510/513 SO16 Pin List SO16 NAME Class 1 Vdd 2 OSCOUT 3 OSCIN 4 Vpp 5 PB0/VREF/AIN0 A 6 PB1/AIN1 A 7 PA7/INT B 8 PA6/T0OUT B 9 PA5/TCLK/ PA4/TSTRT B 11 PA3/ PA2/T1OUT ...

Page 16

ST52510xx ST52513xx Table 1.5 ST52510/513 LFBGA 6X6 Pin List LFBGA36 NAME Class A1 N.C. A2 Vpp A3 VddIO A4 Vss A5 RESET A6 PA0/SCL B B1 N.C. B2 PB0/VREF/AIN0 A B3 OSCIN B4 Vdd B5 VssIO B6 N.C. C1 PB1/AIN1 ...

Page 17

Table 1.6 ST52510/513 SO20 Pin List SO20 NAME Class 1 Vdd 2 OSCOUT 3 OSCIN 4 Vpp 5 PB0/VREF/AIN0 A 6 PB1/AIN1 A 7 PB2/AIN2 A 8 PB3/AIN3 A 9 PB4/AIN4 B 10 PB5/AIN5 B 11 PA7/INT B 12 PA6/T0OUT ...

Page 18

ST52510xx ST52513xx 1.3 Pin Description ST52510/513 pins can be set in digital input mode, digital output mode, interrupt mode or in Alternate Functions. Pin configuration is achieved by means of the configuration registers. The functions of the ST52510/513 pins are ...

Page 19

INTERNAL ARCHITECTURE ST52F510/F513’s architecture is Register File based and is composed of the following blocks and peripherals: Control Unit (CU) ■ Data Processing Unit (DPU) ■ Decision Processor (DP) ■ ALU ■ Memory Interface ■ 256 bytes ...

Page 20

ST52510xx ST52513xx Figure 2.2 Data Processing Unit (DPU) Interrupts Unit Program Memory Input Registers Peripherals REGISTER FILE The DPU receives, stores and sends the instructions deriving from the Program/Data Memory, Register File or from the peripherals controlled by ...

Page 21

Each interrupt level has its own set of flags, which is saved in the Flag Stack during interrupt servicing. These flags are restored from the Flag Stack automatically when a RETI instruction is executed. If the ICU was in normal ...

Page 22

ST52510xx ST52513xx 2.3 Register Description Flags Register (FLAG) Input Register 38 (026h) Read Only Reset Value: 0000 0000 (00h Bit 7-3: Not Used Bit 2: Z Zero flag Bit 1: S Sign flag Bit ...

Page 23

ADDRESSING SPACES ST52F510/F513 has six separate addressing spaces: Register File ■ Program/Data Memory and Stacks ■ Input Registers ■ Output Registers ■ Configuration Registers ■ Fuzzy Registers ■ Note: stack is in the same address space of Program memory. ...

Page 24

ST52510xx ST52513xx NVM is always located beginning after the first locations of the addressing space. RAM banks are always located after NVM. NVM is organized in accordance to the following blocks (see Figure 3.2): Reset Vector block (from address 0 ...

Page 25

Flash and EEPROM are programmed electrically just applying the supply voltage and they are also erased electrically; this feature allows the user to easily reprogram the memory without taking the device off from the board (In Situ Programming ISP). Data ...

Page 26

ST52510xx ST52513xx When a return occurs (RET or RETI instruction), the SSP is increased by 2 and the data stored in the pointed locations couple is restored back into the PC. The current SSP can be read and write in ...

Page 27

Configuration Registers & Option Bytes The ST52F510/F513 Configuration Registers bench consists of a file of 8-bit registers that allows the configuration of all the ICU blocks. The registers are located inside the block they configure in order to obtain ...

Page 28

ST52510xx ST52513xx Table 3.1 Input Registers Mnemonic PORT_A_IN PORT_B_IN PORT_C_IN - - SPI_IN I2C_IN I2C_SR1 I2C_SR2 - - USP_H USP_L - PWM0_COUNT_IN_H PWM0_COUNT_IN_L PWM0_STATUS PWM0_CAPTURE_H PWM0_CAPTURE_L PWM1_COUNT_IN_H PWM1_COUNT_IN_L PWM1_STATUS PWM1_CAPTURE_H PWM1_CAPTURE_L - SCI_IN SCI_STATUS FLAGS AD_OVF IAP_SR 28/136 Description Port ...

Page 29

Table 3.1 Input Registers Mnemonic CHAN0_H CHAN0_L CHAN1_H CHAN1_L CHAN2_H CHAN2_L CHAN3_H CHAN3_L CHAN4_H CHAN4_L CHAN5_H CHAN5_L CHAN6_H CHAN6_L CHAN7_H CHAN7_L Description 10-bit A/D Converter Channel 0 data Input Register (MSB) 10-bit A/D Converter Channel 0 data Input Register (LSB) ...

Page 30

ST52510xx ST52513xx Table 3.2 Output Registers Mnemonic PORT_A_OUT PORT_B_OUT PORT_C_OUT - - SPI_OUT I2C_OUT PWM0_COUNT_OUT_H PWM0_COUNT_OUT_L PWM0_RELOAD_H PWM0_RELOAD_L PWM1_COUNT_OUT_H PWM1_COUNT_OUT_L PWM1_RELOAD_H PWM1_RELOAD_L SCI_OUT Table 3.3 Option Bytes Mnemonic OSC_CR CLK_SET OSC_SET PLDV_CR WDT_EN PG_LOCK PG_UNLOCK WAKEUP 30/136 Description Port A ...

Page 31

Table 3.4 Configuration Registers Mnemonic INT_MASK INT_POL INT_PRL_L INT_PRL_M INT_PRL_H USTP_H USTP_L WDT_CR AD_CR1 PWM0_CR1 PWM0_CR2 PWM0_CR3 PWM1_CR1 PWM1_CR2 - - I2C_CR I2C_CCR I2C_OAR1 I2C_OAR2 SPI_CR SPI_STATUS_CR SCI_CR1 SCI_CR2 PORT_A_PULLUP PORT_A_OR Description Interrupt Mask Register Interrupts Polarity Interrupt Priority Register ...

Page 32

ST52510xx ST52513xx Table 3.4 Configuration Registers Mnemonic PORT_A_DDR PORT_A_AF PORT_B_PULLUP PORT_B_OR PORT_B_DDR PORT_B_AF PORT_C_PULLUP PORT_C_OR PORT_C_DDR PORT_C_AF - SCI_CR3 SSP_H SSP_L CPU_CLK AD_CR2 32/136 Description Port A Data Direction Register Port A Alternate Function selection Register Port B Pull Up ...

Page 33

MEMORY PROGRAMMING ST52F510/F513 provides programmable non-volatile memory, which allows fast and reliable storage of user data. Program/Data Memory addressing space is composed by a Single Voltage Flash Memory and a RAM memory bench. The ST52F513 devices also have a ...

Page 34

ST52510xx ST52513xx 4.2 Memory Programming The Programming procedure writes the user program and data into the Flash Memory, EEPROM and Option Bytes. The programming procedures are entered by setting the V equal to V and releasing the Reset signal. The ...

Page 35

Figure 4.1 Commands and Data Communication Sequences Programming mode start sequence S 10100000 A 00000000 Execution of commands for writing data: Command A Data1 A Execution of commands for reading data: Command A Address A S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From ...

Page 36

ST52510xx ST52513xx A similar procedure can be used to write a single block: 1. The SetPage command is sent, followed by the page number where the data should be written 2. The IncBlock command is sent as many times as ...

Page 37

Figure 4.3 Reading and Erasing Procedures Fast Reading Procedure S 10100000 A 00000000 ..... S 10100000 A ReadData Random Byte Reading Procedure ..... SetPage A Page Address ..... Data read 10100000 Byte Erasing Procedure ..... SetPage A ...

Page 38

ST52510xx ST52513xx 4.3.2 Random data reading. To read a specified memory location, the following procedure should be used: 1. The Programming mode is entered with the sequence described in Section 4.2.1 2. The SetPage command is sent, followed to the ...

Page 39

Figure 4.5 Error Handling Procedure Wrong command/data case handling: Wrong Command/Data A Command/Data 10100000 ..... 10100001 A Status Byte NA P S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge From Slave to Master When the device is locked, if memory reading ...

Page 40

ST52510xx ST52513xx 4.7 In-Situ Programming (ISP) The Program/Data Memory can be programmed using the ISP mode. This mode allows the device to be programmed when it is mounted in the user application board. This feature can be implemented by adding ...

Page 41

Option Bytes. First Protected Page (PG_LOCK) Option Byte 5 (05h) 7 LCK7 LCK6 LCK5 LCK4 LCK3 Bit 7-0: LCK7-0 First Page write protected In this register the address of first page to be protected in writing is specified. The ...

Page 42

ST52510xx ST52513xx 5 INTERRUPTS The Control Unit (CU) responds to peripheral events and external events through its interrupt channels. When such events occur, if the related interrupt is not masked and doesn’t have a priority order, the current program execution ...

Page 43

Interrupt Sources ST52F510/F513 manages generated by the internal peripherals or generated by software by the TRAP instruction or coming from the Port pins. There are two kinds of interrupts coming from the Port pins: the NMI and the Ports ...

Page 44

ST52510xx ST52513xx 5.6 Register Description Interrupt Mask Register (INT_MASK) Configuration Register 0 (00h) Read/Write Reset Value: 0000 0000 (00h) 7 MSKPB MSKPA MSKI2C MSKSPI MSKSCI MSKT1 Bit 7: MSKPB Interrupt Mask Port B 0: Port B interrupt masked 1: Port ...

Page 45

High Priority Register (INT_PRL_H) Configuration Register 4 (04h) Read/Write Reset Value: 1000 1000 (088h) 7 PRL7 PRL6 PRL5 PRL4 PRL3 These three register are used to configure the priority level of each interrupt source. The 24 bits of these registers ...

Page 46

ST52510xx ST52513xx 6 CLOCK, RESET & POWER SAVING MODES 6.1 Clock The ST52F510/F513 Clock Generator module generates the internal clock for the internal Control Unit, ALU and on-chip peripherals. The Clock is designed to require a minimum of external components. ...

Page 47

Reset Four Reset sources are available: RESET pin (external source) ■ WATCHDOG (internal source) ■ POWER ON Reset (Internal source) ■ PLVD Reset (Internal source) ■ When a Reset event occurs, the user program restarts from the beginning. 6.2.1 ...

Page 48

ST52510xx ST52513xx 6.3 Programmable Low Voltage Detector The on-chip Programmable Low Voltage Detector (PLVD) circuit prevents the processor from falling into an unpredictable status if the power supply drops below a certain level. When Vdd drops below the detection level, ...

Page 49

Figure 6.4 HALT Flow Chart HALT INSTRUCTION SKIPPED NO RESET YES OSCILLATOR PERIPHERALS CLOCK CPU CLOCK 4096 INTERNAL CLOCK CYCLES DELAY INTERNAL CLOCK ? NO 4096 X (WAKEUP+1) CLOCK CYCLES DELAY RESET CPU AND RESTART USER PROGRAM HALT INSTRUCTION YES ...

Page 50

ST52510xx ST52513xx 6.5 Register Description The following section describes the Register which are used to configure the Clock, Reset and PLVD. 6.5.1 Configuration Register. CPU Clock Prescaler (CPU_CLK) Configuration Register 46 (02Eh) Read/Write Reset Value: 0000 0000 (00h ...

Page 51

Table 6.1 Recommended Gain Stages for the most common frequencies Recommend Frequency Gain Stages External Clock 0 1 MHz 1 4 MHz 1 8 MHz 3 10 MHz 3 12 MHz 6 16 MHz 6 20 MHz 8 (1) The ...

Page 52

ST52510xx ST52513xx 7 I/O PORTS 7.1 Introduction ST52F510/F513 are characterized by flexible individually programmable multi-functional I/O lines. The ST52F510/F513 supplies devices with Ports (named from with lines. Each pin ...

Page 53

Alternate Functions The Alternate Function allows the pins to be connected with the peripheral signals or NMI. Not all Port pins have an associated. A Configuration Register (PORT_x_AF) for each Port is used to switch from the Digital I/O ...

Page 54

ST52510xx ST52513xx 7.6.1 Configuration Registers. Port A Pull-Up Register (PORT_A_PULLUP) Configuration Register 24 (018h) Read/Write Reset Value: 0000 0000 (00h) 7 PUA7 PUA6 PUA5 PUA4 PUA3 Bit 7-0: PUA7-0 Port A pull-up 0: Port A pin without pull-up 1: Port ...

Page 55

Port B Pull-Up Register (PORT_B_PULLUP) Configuration Register 28 (01Ch) Read/Write Reset Value: 0000 0000 (00h) 7 PUB7* PUB6* PUB5** PUB4** PUB3** PUB2** (*) Pin not available in 16/20 pin package devices. Set to ‘1’ (**) Pin not available in 16 ...

Page 56

ST52510xx ST52513xx Port C Option Register (PORT_C_OR) Configuration Register 33 (021h) Read/Write Reset Value: 0000 0000 (00h ORC5 ORC4 ORC3 Note: The corresponding pins are not available in 16/20 pin devices. Bit 7-6: Not Used Bit 5-0: ...

Page 57

Bit 7-0: PBI7-0 Port B Input data The logical level applied in the Port B pins, configured as digital input, can be achieved by reading this register. Port C Data Input Register (PORT_C_IN) Input Register 2 (02h) Read only Reset ...

Page 58

ST52510xx ST52513xx 8 FUZZY COMPUTATION (DP) The ST52F510/F513 Decision Processor (DP) main features are Inputs with 8-bit resolution; ■ 1 Kbyte of Program/Data Memory available to ■ store more than 300 to Membership Functions (Mbfs) for each ...

Page 59

Figure 8.3 Fuzzyfication IF INPUT INPUT THEN ....... 1 X1 Input Max IF INPUT AND INPUT THEN ....... 1 X1 Input 1 8.4 Defuzzyfication ...

Page 60

ST52510xx ST52513xx Figure 8.5 Example of valid Mbfs 8.6 Output Singleton The Decision Processor uses a particular kind of membership function called Singleton for its output variables. A Singleton doesn’t have a shape, like a traditional Mbf, and is characterized ...

Page 61

Example 1: IF Input IS NOT Mbf AND Input codified by the following instructions: ISNOT 1 1 calculates the NOT FZAND implements the operation AND between the previous and the next alpha value evaluated fixes the value ...

Page 62

ST52510xx ST52513xx 9 INSTRUCTION SET ST52F510/F513 supplies 107 ( Fuzzy) instructions that perform computations and control the device. Computational time required for each instruction consists of one clock pulse for each Cycle plus 2 clock pulses for the ...

Page 63

LDPE LDPE outx, memy LDPE LDPE outx, (regy) LDPI LDPI outx, const LDPR LDPR outx, regy LDRC LDRC regx, const LDRE LDRE regx, memy LDRE LDRE (regx), (regy) LDRE LDRE (regx), memy LDRE LDRE regx, (regy) LDRI LDRI regx, inpx ...

Page 64

ST52510xx ST52513xx DIV DIV regx, regy INC INC regx MIRROR MIRROR regx MULT MULT regx, regy NOT NOT regx OR OR regx, regy ORI ORI regx, const SUB SUB regx, regy SUBI SUBI regx, const SUBIS SUBIS regx, const SUBO ...

Page 65

ROL ROL regx ROR ROR regx RRS RRS regx Mnemonic Instruction CALL CALL addr JP JP addr JPC JPC addr JPNC JPNC addr JPNS JPNS addr JPNZ JPNZ addr JPS JPS addr JPZ JPZ addr RET RET Mnemonic Instruction HALT ...

Page 66

ST52510xx ST52513xx Notes: regx, regy: Register File Address memx, memy: Program/Data Memory Addresses confx, confy: Configuration Registers Addresses outx: Output Registers Addresses inpx: Input Registers Addresses const: Constant value fuzzyx: Fuzzy Input Registers I flag affected - flag not affected ...

Page 67

A/D CONVERTER 10.1 Introduction ST52F510/F513 A/D Converter is a 10-bit analog to digital converter with analog inputs. The A/D converter offers a typical conversion time fast mode and ...

Page 68

ST52510xx ST52513xx external reference mode is chosen the Ain0 channel is not used and the first channel of the conversion sequence becomes Ain1. The converter uses a fully differential analog input configuration for a better noise immunity and precision performances. ...

Page 69

Multiple Channels Continuous Mode. In this mode (CONT=1, SEQ=1) a continuous conversion flow is entered by a start event on the selected channel sequence. The CH2-0 bits indicate the last channel of the sequence. At the end of each ...

Page 70

ST52510xx ST52513xx 10.5.2 Input Registers. A/D Converter Overflow Register (AD_OVF) Input Register 39 (027h) Read only Reset Value: 0000 0000 (00h) 7 OVF7 OVF6 OVF5 OVF4 OVF3 Bit 7-0: OVF7-OVF0 Overflow Flag 0: no overflow occurred in the last conversion ...

Page 71

WATCHDOG TIMER 11.1 Functional Description The Watchdog Timer (WDT) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. ...

Page 72

ST52510xx ST52513xx Watchdog Control Register (WDT_CR) Configuration Register 7 (07h) Read/Write Reset Value: 0000 0001 (01h Bit 7-4: Not Used Table 11.2 Watchdog Timeout configuration examples WDT_CR(3:0) Division Factor 0000 0001 625 0010 1250 ...

Page 73

PWM/TIMERS 12.1 Introduction ST52F510/513 offers two on-chip PWM/Timer peripherals. All ST52F510/513 PWM/Timers have the same internal structure. The timer consists of a 16-bit counter with a 16-bit programmable Prescaler, giving a maximum count of 2 Figure 12.1). Each timer ...

Page 74

ST52510xx ST52513xx Figure 12.2 Timer 0 External Start/Stop Mode Level start E dge R eset C lock C ounted 0 V alue TxSTRT signal starts/stops the Timer from counting only if the peripherals are configured in Timer mode. The Timers ...

Page 75

Figure 12.4 PWM Mode with Reload 65535 Reload Value Counter Value 0 PWM Output 12.3 PWM Mode The PWM working mode for each timer is obtained by setting the TxMOD bit of the Configuration Register PWMx_CR1. The TxOUT signal in ...

Page 76

ST52510xx ST52513xx When the Timers are in Reset status, or when the device is reset, the TxOUT pins goes in threestate. If these outputs are used to drive external devices recommended that the related pins be left in ...

Page 77

PWM/Timer 0 Control Register 2 (PWM0_CR2) Configuration Register 10 (0Ah) Read/Write Reset Value: 0000 0000 (00h T0WAV Bit 7-6: Not Used Bit 5: T0WAV T0OUT Waveform 0: pulse (type2) 1: square (type1) Bit 4-0: T0PRESC PWM/Timer ...

Page 78

ST52510xx ST52513xx PWM/Timer 0 Counter Low Input Register (PWM0_COUNT_IN_L) Input Register 22 (016h) Read only Reset Value: 0000 0000 (00h) 7 T0CI7 T0CI6 T0CI5 T0CI4 T0CI3 Bit 7-0: T0CI7-0 PWM/Timer 0 Counter LSB In this register the current value of ...

Page 79

PWM/Timer 0 Counter Low Output Register (PWM0_COUNT_OUT_L) Output Register 8 (08h) Write only Reset Value: 0000 0000 (00h) 7 T0CO7 T0CO6 T0CO5 T0CO4 T0CO3 Bit 7-0: T0CO7-0 PWM/Timer 0 Counter LSB This register is used to write the Timer 0 ...

Page 80

ST52510xx ST52513xx PWM/Timer 1 Control Register 2 (PWM1_CR2) Configuration Register 13 (0Dh) Read/Write Reset Value: 0000 0000 (00h T1WAV Bit 7-6: Not Used Bit 5: T1WAV T1OUT Waveform 0: pulse (type2) 1: square (type1) Bit 4-0: ...

Page 81

PWM/Timer 1 Capture Low Input Register (PWM1_CAPTURE_L) Input Register 30 (01Eh) Read only Reset Value: 0000 0000 (00h) 7 T1CP7 T1CP6 T1CP5 T1CP4 T1CP3 Bit 7-0: T1CP7-0 PWM/Timer 1 Capture LSB In this register the counter value after the last ...

Page 82

ST52510xx ST52513xx 13 SERIAL COMMUNICATION INTERFACE The Serial Communication integrated into ST52F510/F513 provides a general purpose shift register peripheral, several widely distributed devices to be linked, through their SCI subsystem. SCI gives a serial interface providing communication with the speed ...

Page 83

Recognition of a STOP condition transfers data received from the Recovery Buffer to the SCDR_RX buffer, adding the eventual ninth data bit. After this operation, RXF flag (bit 5) of SCI Status Input Register is set to logic level 1. ...

Page 84

ST52510xx ST52513xx 13.2 SCI Transmitter Block The SCI Transmitter Block consists of the following blocks: SCDR_TX and SHIFT synchronized, respectively, with the clock master signal (fCKM) and the CLOCK_TX. The whole block receives the settings for the following transmission modes ...

Page 85

Table 13.1 Recommended Prescaler values for common frequencies (Baud/MHz 1200 52 208 2400 26 104 4800 13 52 9600 - 26 19200 - 13 38400 - - 57600 - - 115200 - - Table 13.2 Recommended Prescaler values ...

Page 86

ST52510xx ST52513xx 13.4 SCI Register Description The following registers are related to the use of the SCI peripheral. 13.4.1 SCI Configuration Registers. SCI Control Register 1 ( SCI_CR1 Configuration Register 22 (016h) Read/Write Reset Value: 0000 0000 (00h) 7 RXFINT ...

Page 87

SCI Input Registers. SCI RX data Input Register (SCI_IN) Input Register 36 (024h) Read only Reset Value: 0000 0000 (00h) 7 RX7 RX6 RX5 RX4 RX3 Bit 7-0: RX7-0 RX Data In this register the last received serial data ...

Page 88

ST52510xx ST52513xx BUS INTERFACE (I C) 14.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I providing both multimaster and slave functions and 2 controls all ...

Page 89

Acknowledge may be enabled and disabled via software. 2 The I C interface address and/or general call address can be selected via software. 2 The speed of the I C interface may be selected between Standard (0-100KHz) and Fast I ...

Page 90

ST52510xx ST52513xx Note: In 10-bit addressing mode, the comparison includes the header byte (11110xx0) where xx are the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledgement pulse if the ACK bit ...

Page 91

Slave address transmission At this point, the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header ...

Page 92

ST52510xx ST52513xx Figure 14.3 Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 7-bit Master receiver: S Address A EV5 EV6 7-bit Master transmitter: S Address A EV5 EV6 EV8 10-bit ...

Page 93

Figure 14.4 Event Flags and Interrupt Generation ADD10 BTF ADSL SB AF STOPF ARLO BERR * * EVF can also be set by EV6 or an error from the I2C_SR2 register. Interrupt Event 10-bit Address Sent Event (Master Mode) End ...

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ST52510xx ST52513xx 14.5 Register Description In the following sections describe the registers 2 used by the I C Interface are described. 2 14.5 Interface Configuration Registers Control Register (I2C_CR) Configuration Register 16 (010h) Read/Write Reset ...

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Standard I C Mode (recommended up to 100 kHz Fast I C Mode (recommended up to 400 kHz) Bit 6-0: CC6-CC0 7-bit clock divider These bits select the speed of the bus (F 2 depending on ...

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ST52510xx ST52513xx Bit 7: EVF Event Flag This bit is set by hardware as soon as an event occurs cleared by software reading I2C_SR2 register in case of error event or as described in Figure cleared by hardware ...

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Bit 0: SB Start bit (Master Mode) This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE= cleared by software reading I2C_SR1 register followed ...

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ST52510xx ST52513xx 15 SERIAL PERIPHERAL INTERFACE (SPI) 15.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master, one or more slaves system, in which ...

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Figure 15.2 Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS Procedure – Select the SPR0, SPR1 and SPR2 bits to define the serial clock baud rate (see SPI_CR register). – Select the ...

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ST52510xx ST52513xx 15.4.2 Slave Configuration. In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0, SPR1 and SPR2 bits is not used for data transfer. Procedure – For correct ...

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A write collision occurs when the software tries to write to the SPI_OUT register while a data transfer is taking place with an external device. When this occurs, the transfer continues uninterrupted; and the software writing will be unsuccessful. Write ...

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ST52510xx ST52513xx Figure 15.4 Data Clock Timing Diagram CPOL = 1 CPOL = 0 MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MISO MSBit (from master) MOSI MSBit (from ...

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Figure 15.5 Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPI_STATUS_CR 1st Step THEN 2nd Step Read SPI_IN Clearing sequence before SPIF = 1 (during a ...

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ST52510xx ST52513xx Figure 15.6 Single Master Configuration SS SCK Slave MCU MOSI MISO MOSI MISO SCK Master MCU 5V SS 15.4.8 Interrupts Interrupt Event SPI End of Transfer Event Master Mode Fault Event Note: The SPI interrupt events are connected ...

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SPI Register Description In the following sections describe the registers used by the SPI. 15.5.1 SPI Configuration Registers. SPI Control Register (SPI_CR) Configuration Register 20 (014h) Read/Write Reset Value: 0000 0000 (00h) 7 SPIE SPE SPR2 MSTR CPOL Bit ...

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ST52510xx ST52513xx Bit 7: SPIF Serial Peripheral data transfer flag. (read only) This bit is set by hardware when a transfer has been completed. generated if SPIE=1 in the SPI_CR register cleared by a software sequence (an access ...

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Warning: A read to the SPI_IN register returns the value located in the buffer and not the contents of the shift register (see Figure 15.2). 15.5.3 SPI Output Register. SPI Data Output Register (SPI_OUT) Output Register 5 (05h) Write only ...

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ST52510xx ST52513xx 16 ELECTRICAL CHARACTERISTICS 16.1 Parameter Conditions Unless otherwise specified, all voltages are referred to V ss. 16.1.1 Minimum and Maximum values. Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of environment temperature, ...

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Absolute Maximum Ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device under these conditions is not implied. Exposure to maximum rating ...

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ST52510xx ST52513xx 16.3 Operating Conditions Operating condition (unless otherwise specified). A Table 16.4 Operating Conditions Symbol Parameter Operating Supply Voltage in Working mode Operating Supply Voltage in ISP mode Operating Supply Voltage ...

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Supply Current Characteristics Supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the ...

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ST52510xx ST52513xx Table 16.6 Supply Current in RUN, WAIT and SLOW Mode, 2.8 V supply voltage Symbol Parameter Supply current in RUN mode I Supply current in WAIT mode DD Supply current in SLOW mode Notes: 1. CPU running with ...

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Figure 16.4 Typical IDD RUN vs VDD T 12 10,5 9 7,5 6 4,5 3 1,5 0 2,7 3,2 Figure 16.5 Typical IDD WAIT vs VDD T 6 4,5 3 1,5 0 2,7 3,2 = 3,7 4,2 4,7 ...

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ST52510xx ST52513xx 16.5 Clock and Timing Characteristics Operating Conditions 5.5 V, TA=- unless otherwise specified. Values by DD design. Table 16.8 General Timing Parameters Symbol Parameters f Oscillator Frequency osc Minimum External t ...

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Memory Characteristics Operating Conditions 5.5 V, TA=- unless otherwise specified. DD Table 16.10 RAM and Registers Symbol Parameter V RM Data retention mode Table 16.11 Flash Program/Data Memory Symbol Parameter Programming time ...

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ST52510xx ST52513xx 16.8 Programmable Low Voltage Detector (PLVD) Operating Conditions: TA unless otherwise specified. Symbol Parameter Reset release threshold V LVDT rise) DD Reset threshold V LVDT fall Filtered glitch on V ...

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Port Pin Characteristics 16.10.1 General Characteristics Operating Conditions 5.5 V, TA=- unless otherwise specified. DD Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger ...

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ST52510xx ST52513xx Figure 16.8 Port pin Equivalent Circuit 16.10.2 Output Driving Current Operating Conditions 5.5 V, TA=25 C, unless otherwise specified. DD Table 16.13 Output Voltage Levels for class A pins Symbol Parameter Output low level ...

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Control Pins Characteristics 16.11.1 RESET pin. Operating Conditions 5.5 V, TA=25 C, unless otherwise specified. DD Table 16.15 Reset pin Symbol Parameter V Input low level voltage IL V Input high level voltage IH V ...

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ST52510xx ST52513xx 16.12 EMC Characteristics Susceptibility tests are performed on a sample basis during product characterization. 16.12.1 Functional EMS . (Electro Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is ...

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... ESD GENERATOR Notes: 1. Class description: Class STMicroelectronics internal specification. All its limits are higher than the JEDEC specification, that means when a device belongs to Class A it exceeds the JEDEC standard. Class B strictly covers all the JEDEC criteria (international standard). 16.12.5 ESD Pin Protection Strategy. In order ...

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ST52510xx ST52513xx Figure 16.11 Safe discharge path subjected to ESD stress ain path P ath to avoid Figure 16.12 Negative Stress on a Standard Pad vs. VDD VDD Main path VSS 122/136 (3a) ...

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I C Interface Characteristics Subject to general operating conditions for and T unless otherwise specified. osc A, 2 Table 16. Interface Characteristics Symbol Parameter t SCL clock low time w(SCLL) t SCL clock ...

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ST52510xx ST52513xx 16.14 SPI Characteristics Subject to general operating conditions for and T unless otherwise specified. osc A, Symbol Parameter f SPI clock frequency SCK t r(SCK) SPI clock rise and fall time t f(SCK ...

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Figure 16.15 SPI Slave Timing Diagram with CPHA = 0 Figure 16.16 SPI Master Timing Diagram Notes: 1. Measurement points are done at levels: 0.3xV 2. When the SPI is disabled it has its alternate function capability released. In this ...

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ST52510xx ST52513xx 16.15 10-BIT ADC CHARACTERISTICS Operating Conditions 5.5 V, TA=- unless otherwise specified. DD Symbol Parameter f ADC clock frequency ADC V External reference voltage REF R External input resistor AIN R ...

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Figure 16.17 ADC Accuracy Characteristics Digital Result ADCDR 1023 V – V 1022 REF 1LSB = ----------------------------------- 1024 IDEAL 1021 LSB SSA E ...

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ST52510xx ST52513xx 17 SOLDERING INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level in- terconnect. The category of second level intercon- nect is marked on the package and ...

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PACKAGE CHARACTERISTICS 18.1 SO16 Package Data Table 18.1 SO16 PACKAGE MECHANICAL DATA D B DIM MIN A 2.35 A1 0.10 B 0.33 C 0.23 D 10.10 E 7.40 H 10. 0.25 0° ...

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ST52510xx ST52513xx 18.2 SO20 Package Data Table 18.2 SO20 PACKAGE MECHANICAL DATA DIM MIN A 2.35 A1 0.1 B 0.33 C 0.23 D 12 0.25 L 0.4 0° 130/136 mm TYP. MAX ...

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SO28 Package Data Table 18.3 SO28 PACKAGE MECHANICAL DATA DIM MIN A 2.35 A1 0.10 B 0.33 C 0.23 D 17. 10.00 h 0.25 0° TYP. MAX 2.65 0.30 0.51 ...

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ST52510xx ST52513xx 18.4 SDIP32 Package Data Table 18.4 SDIP32 PACKAGE MECHANICAL DATA DIM MIN A 3.56 A1 0.51 A2 3.05 b 0.36 b1 0.76 C 0.20 D 27.43 E 9. ...

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LFBGA36 Package Data Table 18.5 LFBGA36 PACKAGE MECHANICAL DATA DIM MIN A 1.210 A1 0.270 A2 b 0.450 D 5.750 D1 E 5.750 E1 e 0.720 f 0.850 ddd mm TYP. MAX 1.700 1.120 0.500 0.550 6.000 6.150 4.000 ...

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ST52510xx ST52513xx 19 IMPORTANT NOTES 19.1 SILICON IDENTIFICATION This document describes the limitations that apply to ST52F510/F513 devices, silicon revision U. This is identifiable on: Device package, by the last letter of Trace Code marked on device package. On the ...

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REVISION HISTORY Table 20.1 Document revsion history Date Revision April 04 2.1 April 04 2.2 May 04 2.3 Apr 08 16 July 08 17 Description of Changes Table 4.1 Sales Type Memory Organization on page 33 Table 4.3 Error ...

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... ST52510xx, ST52513xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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