STA333BW STMicroelectronics, STA333BW Datasheet
STA333BW
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STA333BW Summary of contents
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... Thermal overload and short-circuit protection technology Video apps: 576 x f Pin and SW compatible with STA335BW, STA339BW, STA339BWS, STA559BW and STA559BWS Package PowerSSO-36 EPD PowerSSO-36 EPD Doc ID 13773 Rev 3 STA333BW Sound Terminal® PowerSSO-36 with exposed pad down (EPD interface input mode supported S Packaging Tube ...
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... Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.1 5.4.2 5.4.3 5.4.4 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/67 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 13773 Rev 3 STA333BW ...
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... STA333BW 6.1 Configuration registers (addr 0x00 to 0x05 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Volume control registers (addr 0x06 - 0x0A 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 Audio preset registers (addr 0x0B and 0x0C 6.3.1 6.3.2 6.4 Channel configuration registers (addr 0x0E - 0x10 ...
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... Contents 6.11 Device status register (addr 0x2D Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4/67 Doc ID 13773 Rev 3 STA333BW ...
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... STA333BW List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Pin connection PowerSSO-36 (top view Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Left and right processing, section Figure 7. Left and right processing, section Figure 8. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9. ...
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... Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 42. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 43. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 44. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 45. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 46. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 47. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 48. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6/67 Doc ID 13773 Rev 3 STA333BW ...
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... STA333BW Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 50. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 51. Master volume offset as a function of MVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 52. Channel volume as a function of CxVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 53. Audio preset gain compression / limiters selection for AMGC[3: Table 54. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 55. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 56 ...
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... The high-quality conversion from PCM audio to FFX PWM switching provides over 100 dB of SNR and of dynamic range. Also provided in the STA333BW are a full assortment of digital processing features. This includes programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings ...
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... STA333BW 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B / FFX3B OUT3A / FFX3A 2.2 Pin description Table 2. Pin description Pin Type 1 GND I GND 8 Power VSS 5 6 OUT2B 7 GND2 8 VCC2 9 OUT2A OUT1B 10 VCC1 ...
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... S left / right clock 2 SDI I S serial data channels 1 and 2 RESET Reset (pull-up) INT_LINE Fault interrupt 2 SDA I C serial data 2 SCL I C serial clock GND_DIG Digital ground VDD_DIG Digital supply voltage EP Exposed pad for PCB heatsink connected to GND Doc ID 13773 Rev 3 STA333BW Description ...
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... STA333BW 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG PLL supply voltage (pin VDD_PLL Operating junction temperature op T Storage temperature stg Warning: 3.2 Thermal data Table 4. Thermal data ...
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... Low level output voltage ol V High level output voltage oh Equivalent pull-up/down R pu resistance 12/67 Parameter Parameter Conditions VDD_DIG = 3 Iol = 2 mA Ioh = Doc ID 13773 Rev 3 STA333BW Min Typ Max 4.5 - 21.5 2.7 3.3 3.6 2.7 3.3 3.6 - °C unless otherwise specified. amb Min Typ Max - ...
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... STA333BW 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol Parameter Output power BTL Po Output power SE R Power P-channel or N-channel MOSFET dsON gP Power P-channel R ...
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... Electrical specifications Figure 3. Test circuit Duty cycle = 50% INxY 14/67 OUTxY tr +Vcc M58 Ω OUTxY R 8 M57 gnd Doc ID 13773 Rev 3 STA333BW VCC (0.9)*VCC ½VCC (0.1)*VCC V67 - vdc = Vcc/2 ...
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... STA333BW 3.6 Power-on/off sequence Figure 4. Power-on sequence VCC VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI XTI Reset Reset Reset Reset Reset PWDN PWDN PWDN PWDN PWDN TR = minimum time between XTI master clock stable and Reset removal ...
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... A prescaler and a final postscaler allow full control over the signal dynamics before and after the filtering stages. A mixer function is also available. 16/67 below show the data processing paths inside STA333BW. The whole Figure 6, begins with a 2x oversampling FIR filter providing Sampling ...
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... STA333BW Figure 7. Left and right processing, section C1Mx1 C1Mx1 Hi-Pass Hi-Pass Filter Filter C1Mx2 C1Mx2 C2Mx1 C2Mx1 Hi-Pass Hi-Pass Filter Filter C2Mx2 C2Mx2 C3Mx1 C3Mx1 Lo-Pass Lo-Pass Filter Filter C3Mx2 C3Mx2 User-Defined Mix Coefficients User-Defined Mix Coefficients Crossover Frequency determined by XO Setting ...
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... The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333BW is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate). ...
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... After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. Figure 9. ...
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... STA333BW 6 Register description Note: Addresses exceeding the maximum address number must not be written. Table 8. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF EAPD 0x06 MUTELOC LOC1 0x07 MVOL ...
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... R/W 2 R/W The STA333BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz ...
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... Bit R/W 4:3 R/W The STA333BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. ...
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... RST Name 0: thermal warning adjustment enabled TWAB 1: thermal warning adjustment disabled RST Name 0: fault detect recovery enabled FDRB 1: fault detect recovery disabled D5 D4 DSCKE SAIFB 0 0 Doc ID 13773 Rev 3 STA333BW Description Description Description SAI3 SAI2 SAI1 SAI0 0 ...
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... Serial data interface The STA333BW audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA333BW always acts as slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI. ...
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... Right-justified 24-bit data 0110 1 Right-justified 20-bit data 1010 1 Right-justified 18-bit data 1110 1 Right-justified 16-bit data Doc ID 13773 Rev 3 STA333BW Interface format Interface Format S 15-bit data S 23-bit data S 20-bit data S 18-bit data 2 S 16-bit data S 24-bit data S 20-bit data S 18-bit data 2 ...
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... STA333BW To make the STA333BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that: N-4< = (frequency of PLL clock) / (frequency of LRCKI) = < N+4 cycles, where N depends on the settings in the PLL must be locked. If these two conditions are not met, and IDE bit (register 0x05, bit 2) is set to 1, the STA333BW immediately mutes the I it freezes any active processing task ...
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... R/W 1 The OCRB is used to indicate how STA333BW behaves when an overcurrent warning condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control block forces an adjustment to the modulation limit (default attempt to eliminate the overcurrent warning condition. Once the overcurrent warning clipping adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1 ...
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... High-pass filter bypass Bit R/W 0 R/W 0 The STA333BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled. De-emphasis Table 27. De-emphasis ...
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... DRC 1: limiters act in dynamic range compression mode RST Name 0: automatic zero-detect mute disabled ZDE 1: automatic zero-detect mute enabled RST Name 0: submix into left / right disabled SME 1: submix into left / right enabled Doc ID 13773 Rev 3 STA333BW Description Description Description Description ...
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... R/W 1 Setting the MPC bit turns on special processing that corrects the STA333BW power device at high power. This mode should lower the THD full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC has no effect on channels 3 and 4, the line-out channels ...
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... DCC coefficient Name 1: volume adjustments only occur at digital zero- crossings ZCE 0: volume adjustments occur immediately Name 1: volume adjustments ramp according to SVUP / SVDW settings SVE 0: volume adjustments occur immediately ECLE LDTE BCLE Doc ID 13773 Rev 3 STA333BW Description Description Description Description IDE OCFG1 OCFG0 ...
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... STA333BW Output configuration Table 42. Output configuration Bit R R/W 0 Table 43. Output configuration engine selection OCFG[1: Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. ...
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... Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half Bridge Bridge Channel 2 Channel 2 Half Half Bridge Bridge OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B Power Power Channel 3 Channel 3 Device Device EAPD EAPD Doc ID 13773 Rev 3 STA333BW ...
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... STA333BW Figure 13. OCFG = 11 The STA333BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries. ...
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... EQ have no effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 15. 2.0 channels (OCFG = 00) PWM slots 36/67 OUT1A OUT1A OUT1B OUT1B OUT2A OUT2A OUT2B OUT2B OUT3A OUT3A OUT3B OUT3B OUT4A OUT4A OUT4B OUT4B Doc ID 13773 Rev 3 STA333BW Figure 15. ...
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... STA333BW 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping: FFX1A -> OUT1A FFX2A -> OUT1B FFX3A -> OUT2A FFX3B -> OUT2B FFX1A -> OUT3A FFX1B -> OUT3B FFX2A -> OUT4A FFX2B -> OUT4B Modulation: FFX1A / 1B configured as binary FFX2A / 2B configured as binary FFX3A / 3B configured as binary FFX4A / 4B configured as binary In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3 / OUT4 channels the channel 1 and channel 2 PWM are replicated ...
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... In this configuration the PWM slot phase is the following as shown in Figure 17. 2.1 channels (OCFG = 10) PWM slots OUT1A OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT1B OUT2A OUT2A OUT2A OUT2A OUT2B OUT2B OUT2B OUT2B OUT3A OUT3A OUT3A OUT3A OUT3B OUT3B OUT3B OUT3B 38/67 Doc ID 13773 Rev 3 STA333BW Figure 17. ...
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... STA333BW Invalid input detect mute enable Table 44. Invalid input detect mute enable Bit R/W 2 R/W 1 Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as invalid. Binary output mode clock loss detection Table 45. Binary output mode clock loss detection ...
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... FFX4B / EAPD output pin when OCFG = 10. 6.2 Volume control registers (addr 0x06 - 0x0A) The volume structure of the STA333BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -80 dB ...
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... STA333BW 6.2.1 Mute / line output configuration register (addr 0x06 LOC1 LOC0 0 0 Table 50. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. ...
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... D5 D4 C3VOL5 C3VOL4 C3VOL3 1 0 +48 dB +47.5 dB +47 dB … +0 -0.5 dB … -59.5 dB -60 dB -61 dB -62 dB … -80 dB Hard channel mute … Hard channel mute Doc ID 13773 Rev 3 STA333BW C3VOL2 C3VOL1 Volume D0 C3VOL0 0 ...
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... STA333BW 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B Reserved Reserved 1 0 Using AMGC[1:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. They are defined below in Table 53. ...
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... A 1st-order hign-pass filter (channels 1 and 2nd-order low-pass filter (channel 3) at the selected XO2 frequency is performed. XO3 Crossover frequency User-defined (Section 6.7.8 on page 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz Doc ID 13773 Rev 3 STA333BW Description 55) ...
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... STA333BW 6.4 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 Tone control bypass Tone control (bass / treble) can be bypassed on a per channel basis for channels 1 and 2. Table 58. Tone control bypass CxTCB bypass EQ control can be bypassed on a per channel basis for channels 1 and control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel ...
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... Table 63. Channel output mapping as a function of CxOM bits CxOM[1: 46/67 FFX output operation Binary output Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 Channel x output source from Channel1 Channel 2 Channel 3 Doc ID 13773 Rev 3 STA333BW Mode ...
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... STA333BW 6.5 Tone control register (addr 0x11 TTC3 TTC2 0 1 Tone control Table 64. Tone control boost / cut as a function of BTC and TTC bits BTC[3:0], TTC[3:0] 0000 0001 0010 … 0101 0110 0111 1000 1001 … 1100 1101 1110 1111 6.6 Dynamic control registers (addr 0x12 - 0x15) 6 ...
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... It is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a FFX amplifier. Since gain can be added digitally within the STA333BW it is possible to exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter ...
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... STA333BW reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless” mode, the attack and release thresholds are set relative to full-scale. In DRC mode, ...
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... Release Rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 AC (dB relative to fs) -12 - Doc ID 13773 Rev 3 STA333BW Fast Slow ...
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... STA333BW Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] 1110 1111 Table 68. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Dynamic range compression mode Table 69. ...
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... Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 52/67 DRC (dB relative to Volume) -15 -14 -13 -12 - DRC (db relative to Volume + LxAT) -∞ -38 -36 -33 -31 -30 -28 -26 -24 -22 -20 -18 -15 - Doc ID 13773 Rev 3 STA333BW ...
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... STA333BW 6.7 User-defined coefficient control registers (addr 0x16 - 0x26) 6.7.1 Coefficient address register (addr 0x16 Reserved Reserved 0 0 6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19 C1B23 C1B22 C1B15 C1B14 C1B7 C1B6 0 0 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) ...
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... D5 D4 C5B13 C5B12 C5B11 C5B5 C5B4 Reserved 0 Doc ID 13773 Rev C3B3 C3B2 C3B1 C4B18 C4B17 C4B10 C4B9 C4B3 C4B2 C4B1 C5B18 C5B17 C5B10 C5B9 C5B3 C5B2 C5B1 STA333BW D0 C3B0 0 D0 C4B16 0 D0 C4B8 0 D0 C4B0 0 D0 C5B16 0 D0 C5B8 0 D0 C5B0 ...
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... Description Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA333BW via RAM. Access to this RAM is available to the user via an I register interface. A collection of I coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read / write of the coefficient(s) to/from RAM ...
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... When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example 10, 20, 35 decimal), and the STA333BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data. Table 71. ...
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... User-defined EQ The STA333BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0 ...
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... Prescale The STA333BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiply is loaded into RAM ...
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... STA333BW 6.8 Variable max power correction registers (addr 0x27 - 0x28 MPCC15 MPCC14 MPCC7 MPCC6 1 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 6.9 Distortion compensation registers (addr 0x29 - 0x2A DCC15 ...
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... VCCxX internally detected UVFAULT < undervoltage threshold Reserved - OCFAULT 0: overcurrent fault detected OCWARN 0: overcurrent warning TFAULT 0: thermal fault, junction temperature over limit 0: thermal warning, junction temperature is close to TWARN the fault condition Doc ID 13773 Rev OCFAULT OCWARN TFAULT Description STA333BW D0 TWARN ...
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... Applications 7.1 Applications schematic Figure 20 below shows the typical applications schematic for STA333BW. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. 7.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications ...
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... Figure 20. Applications circuit C14 100µF 25V C18 100nF C21 1µF 25V OUT2B OUT2A C23 100nF Vcc OUT1B C29 100nF OUT1A C31 1µF 25V C32 100nF 3V3 STA333BW GND_SUB VDD_DIG GND_DIG 3 34 SCL TEST_MODE SCL 4 33 SDA VSS SDA 5 32 INTL ...
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... Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. Thus, the maximum estimated dissipated power for the STA333BW is Ω Ω, 8 Ω Figure 21 ...
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... Doc ID 13773 Rev 3 STA333BW gives the dimensions. Dimensions in inches Min Typ 0.085 - 0.097 0.085 - 0.094 0.00 - 0.004 0.007 - 0.014 0.009 - 0.013 0.398 - 0.413 0.291 - 0.299 - 0.020 - - 0.335 - - 0.091 - ...
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Figure 22. PowerSSO-36 EPD outline drawing h x 45° ...
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... Absolute maximum ratings Recommended operative conditions Output configuration Device status register Updated presentation Document status updated to Datasheet 3 Modified layout of chapter Removed master mute from Improved presentation of applications circuit in Doc ID 13773 Rev 3 STA333BW Changes Chapter 1: Description Section 6.2 on page 40 Figure 20 on page 62 ...
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... STA333BW Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...