ISP1761BE STEricsson, ISP1761BE Datasheet
ISP1761BE
Specifications of ISP1761BE
Available stocks
Related parts for ISP1761BE
ISP1761BE Summary of contents
Page 1
IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
Page 2
ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller Rev. 05 — 13 March 2008 1. General description The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with advanced NXP slave host controller and the NXP ISP1582 ...
Page 3
NXP Semiconductors I Separate IRQ, DREQ and DACK lines for the host controller and the peripheral controller I Integrated multi-configuration FIFO I Double-buffering scheme increases throughput and facilitates real-time data transfer I Integrated Phase-Locked Loop (PLL) with external 12 MHz ...
Page 4
NXP Semiconductors N Slave DMA, fully autonomous and supports multiple configurations N Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint N Integrated 8 kB memory N Software-controllable connection to the USB bus, SoftConnect 3. ...
Page 5
... Ordering information Table 1. Ordering information Type number Package Name Description ISP1761BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 ISP1761ET TFBGA128 plastic thin fine-pitch ball grid array package; 128 balls; body 9 ISP1761_5 Product data sheet Rev. 05 — 13 March 2008 ...
Page 6
... This figure shows the LQFP pinout. For the TFBGA ballout, see All ground pins should normally be connected to a common ground plane. Fig 1. Block diagram ISP1761_5 Product data sheet V CC(I/O) 10, 40, 48, 59, 67, 75, 83, 94, 104, 115 ISP1761BE SEL16/32 HC PTD MEMORY (3 kB) BUS INTERFACE: HC PAYLOAD MEMORY MEMORY MANAGEMENT ...
Page 7
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. ISP1761_5 Product data sheet 1 ISP1761BE 38 Pin configuration (LQFP128); top view ball A1 index area Pin configuration (TFBGA128); top view Rev. 05 — 13 March 2008 Hi-Speed USB OTG controller 102 65 004aaa506 ISP1761ET 004aaa551 © NXP B.V. 2008. All rights reserved. ...
Page 8
NXP Semiconductors 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin LQFP128 TFBGA128 OC3_N 1 C2 REF5V GNDA 4 A1 REG1V8 CC(5V0 CC(5V0) GND(OSC ...
Page 9
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 PSW2_N 28 M1 GND(RREF3 RREF3 30 N1 [6] GNDA 31 P2 DM3 32 P1 GNDA 33 R2 DP3 34 R1 PSW3_N 35 T1 GNDD 36 T2 ...
Page 10
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA9 49 T8 REG1V8 50 R8 DATA10 51 P9 DATA11 52 T9 GNDC 53 R9 DATA12 54 T10 GNDD 55 R10 DATA13 56 P11 DATA14 57 T11 DATA15 ...
Page 11
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 DATA21 66 R15 V 67 P15 CC(I/O) DATA22 68 T16 DATA23 69 R16 DATA24 70 P16 GNDD 71 N16 DATA25 72 N15 DATA26 73 M15 DATA27 74 M16 ...
Page 12
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 A2 84 H15 REG1V8 85 G16 A3 86 H14 A4 87 F16 GNDC 88 G15 A5 89 F15 GNDD 90 E16 A6 91 F14 A7 92 E15 A8 ...
Page 13
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 CS_N 106 A12 RD_N 107 B12 WR_N 108 B11 GNDD 109 A11 BAT_ON_N 110 C10 DC_IRQ 111 A10 HC_IRQ 112 B10 DC_DREQ 113 A9 HC_DREQ 114 B9 V ...
Page 14
NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin LQFP128 TFBGA128 RESET_N 122 B6 GNDA 123 B5 C_B 124 A5 C_A 125 B4 V 126 A4 CC(C_IN) OC1_N/V 127 B3 BUS OC2_N 128 A3 [1] Symbol names ending with ...
Page 15
NXP Semiconductors 7. Functional description 7.1 ISP1761 internal architecture: advanced NXP slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave host controller. The EHCI is the ...
Page 16
NXP Semiconductors Fig 4. 7.1.1 Internal clock scheme and port selection Figure 5 Fig 5. ISP1761_5 Product data sheet EHCI ROOT HUB PORTSC1 ENUMERATION AND POLLING USING ACTUAL PTDs INTERNAL HUB (TT) PORT2 PORT1 Internal hub shows the internal clock ...
Page 17
NXP Semiconductors Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the ...
Page 18
NXP Semiconductors The total amount of memory allocated to the payload determines the maximum transfer size specifi PTD, a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context ...
Page 19
NXP Semiconductors The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its ...
Page 20
NXP Semiconductors 63 kB USB HIGH-SPEED USB BUS HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED) Fig 6. Memory segmentation and access block diagram Both the CPU interface logic and the USB host controller require access to the internal ISP1761 RAM ...
Page 21
NXP Semiconductors access must always be completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In ...
Page 22
NXP Semiconductors 7.3.3 PIO mode access, register read cycle The PIO register read access is similar to a general register access not necessary to set a pre-fetching address before a register read. The ISP1761 register read address will ...
Page 23
NXP Semiconductors It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1761 memory. The ISP1761 will be accessed in PIO mode. Consequently, memory read operations must be preceded ...
Page 24
NXP Semiconductors 3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match IRQ settings of the host processor. By default, interrupt is level-triggered and active ...
Page 25
NXP Semiconductors With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer (ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will be generated when the AND ...
Page 26
NXP Semiconductors The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation. 7.6 Power management The ISP1761 implements ...
Page 27
NXP Semiconductors count, the ISP1761 will switch back to suspend mode after the specified time. The maximum delay that can be programmed in the clock-off count field is approximately 500 ms. Additionally, the Power Down Control register allows ISP1761 internal ...
Page 28
... CC(5V0 10, 40, 48, CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 ISP1761BE REG1V8 5, 50, 118 REG3V3 9 V CC(C_IN) 126 This figure shows the LQFP pinout. For the TFBGA ballout, see A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 118. All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 ISP1761 power supply connection shows the most commonly used power supply connection ...
Page 29
... In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current CC(5V0) back on, before the resume programming sequence starts. ISP1761_5 Product data sheet ISP1761BE 6, 7, 10, 40, V CC(5V0) 48, 59, 67, 75, 83, 94, 104, 115, 126 REG1V8 ...
Page 30
... CC(5V0 10, 40, 48, CC(I/O) 59, 67, 75, 83, 94, 104, 115 REG1V8 85 ISP1761BE REG1V8 5, 50, 118 REG3V3 9 V CC(C_IN) 126 This figure shows the LQFP pinout. For the TFBGA ballout, see A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 118. All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Hybrid mode shows the status of output pins during hybrid mode ...
Page 31
NXP Semiconductors For an overcurrent limit of 500 mA per port, a PMOS transistor with R approximately 100 m is required PMOS transistor with a lower R analog overcurrent detection can be adjusted using a series resistor; see ...
Page 32
NXP Semiconductors The internal POR pulse will be generated whenever V than 11 s. (1) PORP = Power-On Reset Pulse. Fig 11. Internal power-on reset timing The recommended RESET input pulse length at power-on must be at least 2 ms ...
Page 33
NXP Semiconductors 8. Host controller Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. • Operational registers range from 0000h to 01FFh. Host controller-specific and ...
Page 34
NXP Semiconductors Table 8. Address 033Ch 0340h 0344h 0354h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. ...
Page 35
NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol PRR Reset 0 Access R Table 12. Bit ...
Page 36
NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 1 Access R Table 14. Bit ...
Page 37
NXP Semiconductors Table 15. USBCMD - USB Command register (address 0020h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol ...
Page 38
NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 18. ...
Page 39
NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
Page 40
NXP Semiconductors Table 22. Bit [1] For details on register bit description, refer to Universal Serial Bus Rev. 8.2.6 PORTSC1 register The Port Status and Control (PORTSC) register (bit allocation: well reset by ...
Page 41
NXP Semiconductors Table 24. Bit [1] For details on register bit description, refer to Universal Serial ...
Page 42
NXP Semiconductors 8.2.8 ISO PTD Skip Map register Table 26 Table 26. ISO PTD Skip Map register (address 0134h) bit description Bit Symbol Access ISO_PTD_SKIP R/W _ MAP[31:0] When a bit in the PTD Skip Map is ...
Page 43
NXP Semiconductors Table 29. INT PTD Skip Map register (address 0144h) bit description Bit Symbol Access INT_PTD_SKIP_ R/W MAP[31:0] When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped ...
Page 44
NXP Semiconductors When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not ...
Page 45
NXP Semiconductors [1] The reserved bits should always be written with the reset value. Table 35. Bit ISP1761_5 Product data ...
Page 46
NXP Semiconductors Table 35. Bit 8.3.2 HcChipID register Read this register to get the ID of the ISP1761. This upper word of the register contains the hardware version number and the lower word contains the chip ID. ...
Page 47
NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 39. Bit 8.3.5 HcDMAConfiguration ...
Page 48
NXP Semiconductors [1] The reserved bits should always be written with the reset value. Table 41. Bit DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read ...
Page 49
NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 43. Bit 8.3.7 ...
Page 50
NXP Semiconductors The bit description of the register is given in Table 45. Memory register (address 033Ch) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 ...
Page 51
NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 48. Bit ...
Page 52
NXP Semiconductors Table 50. Bit 8.3.11 Power Down Control register This register is used to turn off power to internal blocks of the ISP1761 to obtain maximum power savings. Table 51. Power Down Control ...
Page 53
NXP Semiconductors Table 52. [1] Bit ISP1761_5 Product data sheet Power Down Control register (address 0354h) bit description Symbol Description CLK_OFF_ Clock Off Counter: Determines ...
Page 54
NXP Semiconductors Table 52. [1] Bit [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write ...
Page 55
NXP Semiconductors Bit 7 Symbol INT_IRQ CLK READY Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 54. Bit ISP1761_5 Product data ...
Page 56
NXP Semiconductors Table 54. Bit 8.4.2 HcInterruptEnable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 55. HcInterruptEnable - Host Controller Interrupt Enable register ...
Page 57
NXP Semiconductors Bit 7 Symbol INT_IRQ_E CLKREADY Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 56. Bit ISP1761_5 Product data ...
Page 58
NXP Semiconductors Table 56. Bit 8.4.3 ISO IRQ MASK OR register Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done ...
Page 59
NXP Semiconductors Table 59. ATL IRQ Mask OR register (address 0320h) bit description Bit Symbol Access Value ATL_IRQ_MASK_ R/W OR[31:0] 8.4.6 ISO IRQ MASK AND register Each bit of this register corresponds to one of the 32 ...
Page 60
NXP Semiconductors The PTD structures of the ISP1761 are translations of EHCI data structures that are optimized for the ISP1761. It, however, still follows the basic EHCI architecture. This optimized form of EHCI data structures is necessary because the ISP1761 ...
Page 61
NXP Semiconductors 5. If combined with skip, the skip must not be set (logically) on the same position corresponding to NextPTD, pointed by the NextPTD pointer PTD is set for skip, it will be neglected and the next ...
Page 62
High-speed bulk IN and OUT Table 63 shows the bit allocation of the high-speed bulk IN and OUT, asynchronous Transfer Descriptor. Table 63. High-speed bulk IN and OUT: bit allocation Bit ...
Page 63
NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - 5 J ...
Page 64
NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - 46 ...
Page 65
NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes - MaxPacket SW — writes - Length[10: NrBytesTo SW — writes - Transfer[14:0] ...
Page 66
High-speed isochronous IN and OUT Table 65 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD). Table 65. High-speed isochronous IN and OUT: bit allocation Bit ...
Page 67
NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ...
Page 68
NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW3 — sets — writes — writes reserved - NrBytes HW ...
Page 69
NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — resets ...
Page 70
High-speed interrupt IN and OUT Table 67 shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD). Table 67. High-speed interrupt IN and OUT: bit allocation Bit ...
Page 71
NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 ...
Page 72
NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — ...
Page 73
NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: ...
Page 74
Start and complete split for bulk Table 70 shows the bit allocation of Start Split (SS) and Complete Split (CS) for bulk, asynchronous Start Split and Complete Split (SS/CS) Transfer Descriptor. Table 70. Start and complete split for bulk: ...
Page 75
NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer[4:0] ...
Page 76
NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol NrBytes Transferred[14:0] DW2 reserved RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 ...
Page 77
NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol MaximumPacket Length[10: NrBytesTo Transfer[14: reserved 0 V Table 72. Bulk I/O I/O ISP1761_5 Product data sheet …continued ...
Page 78
Start and complete split for isochronous Table 73 shows the bit allocation for start and complete split for isochronous, split isochronous Transfer Descriptor (siTD). Table 73. Start and complete split for isochronous: bit allocation Bit ...
Page 79
NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] ...
Page 80
NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes 59 ...
Page 81
NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access Device SW — writes Address[6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved ...
Page 82
Start and complete split for interrupt Table 75 shows the bit allocation of start and complete split for interrupt. Table 75. Start and complete split for interrupt: bit allocation Bit ...
Page 83
NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] ...
Page 84
NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access SA[7:0] SW — writes (0 HW — writes (1 After processing DW3 — sets HW — resets 62 H ...
Page 85
NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access 47 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — writes ...
Page 86
NXP Semiconductors 9. OTG controller 9.1 Introduction OTG is a supplement to the Hi-Speed USB specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted at ...
Page 87
NXP Semiconductors peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature ...
Page 88
NXP Semiconductors 9.4 Host Negotiation Protocol (HNP) HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role ...
Page 89
NXP Semiconductors 6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off V ...
Page 90
NXP Semiconductors START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 15. Dual-role A-device state diagram ISP1761_5 ...
Page 91
NXP Semiconductors START id/ | b_sess_vld/ b_host chrg_vbus/ loc_conn/ loc_sof a_conn b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ Fig 16. Dual-role B-device state diagram 9.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality. ...
Page 92
NXP Semiconductors 2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt Enable Fall registers. 3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10). 4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit ...
Page 93
NXP Semiconductors Table 80. Address OTG Timer register 0388h 038Ch Table 81. Address Device ID registers 0370h 0372h OTG Control register 0374h 0376h OTG Interrupt registers 0378h 037Ah 037Ch 037Eh 0380h 0382h 0384h 0386h OTG Timer register 0388h 038Ah 038Ch ...
Page 94
NXP Semiconductors 9.5.2 OTG Control register 9.5.2.1 OTG Control register Table 84 Table 84. OTG Control register (address set: 0374h, clear: 0376h) bit allocation Bit 15 Symbol Reset 0 Access R/S/C R/S/C Bit 7 Symbol SW_SEL_ VBUS_ HC_DC CHRG Reset ...
Page 95
NXP Semiconductors Table 85. [1] Bit [1] To use port host controller, write 0080 0018h to this register after power-on. To use port peripheral controller, write 0006 0400h to this register ...
Page 96
NXP Semiconductors Table 87. Bit 9.5.3.2 OTG Interrupt Latch register The OTG Interrupt Latch register indicates the source that generated the interrupt. The status of this register bits depends on the ...
Page 97
NXP Semiconductors 9.5.3.3 OTG Interrupt Enable Fall register Table 90 HIGH-to-LOW. Table 90. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit allocation Bit 15 Symbol Reset 0 Access R/S/C R/S/C Bit 7 Symbol B_SESS_ END Reset 0 ...
Page 98
NXP Semiconductors Bit 7 Symbol B_SESS_ BDIS_ END ACON Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 93. Bit ...
Page 99
NXP Semiconductors Bit 7 Symbol Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 95. Bit ISP1761_5 Product data sheet TIMER_INIT_VALUE[7:0] ...
Page 100
NXP Semiconductors 10. Peripheral controller 10.1 Introduction The design of the peripheral controller in the ISP1761 is compatible with the NXP ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the peripheral controller in the ISP1761 is similar ...
Page 101
NXP Semiconductors peripheral controller. If DMA is not required by the application, DMACLKON can be permanently disabled to save current. The burst counter, DMA bus width, and the polarity of DC_DREQ and DC_DACK must accordingly be set. The ISP1761 supports ...
Page 102
NXP Semiconductors If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or empty packet is received. This means that DMA transfer terminated. Normally, for an OUT transfer, it means that remote host wishes ...
Page 103
NXP Semiconductors Table 96. Endpoint identifier EP6TX EP7RX EP7TX 10.3 Clear buffer Use clear buffer when data needs to be discarded under the following conditions: • IN endpoint: If the host aborts a read operation, the residual data in the ...
Page 104
NXP Semiconductors • In 32-bit bus access mode, the register addresses are 4 bytes aligned. Therefore, the DcBufferStatus register can be accessed using the upper-two bytes of the Buffer Length register. • The SOFTCT bit in the Mode register has ...
Page 105
NXP Semiconductors Table 97. Address Register 0228h 0220h 021Ch 021Eh 0204h 0208h DMA registers 0230h 0234h 0238h 023Ch 0250h 0254h 0258h 0264h General registers 0218h 0270h 0274h 0278h 027Ch 0280h 0284h 10.5.1 Address register This register sets the USB assigned ...
Page 106
NXP Semiconductors Table 99. Bit 10.5.2 Mode register This register consists of 2 bytes (bit allocation: see The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset and clock signals. Table 100. Mode ...
Page 107
NXP Semiconductors Table 101. Mode register (address 020Ch) bit description Bit 10.5.3 Interrupt Configuration register This 1 byte register determines the behavior and polarity of the INT output. The bit allocation is ...
Page 108
NXP Semiconductors Table 103. Interrupt Configuration register (address 0210h) bit description Bit Symbol CDBGMOD[1: DDBGMODIN[1: DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see 1 INTLVL 0 INTPOL Table 104. Debug mode ...
Page 109
NXP Semiconductors 10.5.5 DcInterruptEnable register This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits, here n represents the endpoint number. All interrupts can globally be ...
Page 110
NXP Semiconductors Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) Bit ...
Page 111
NXP Semiconductors • Endpoint MaxPacketSize • Endpoint Type For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the Endpoint Index register must be written first with 02h. Remark: The Endpoint Index register and ...
Page 112
NXP Semiconductors Table 112. Control Function register (address 0228h) bit allocation Bit 7 Symbol reserved Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 113. Control Function register ...
Page 113
NXP Semiconductors 10.6.3 Data Port register This register provides direct access for a microcontroller to the FIFO of the indexed endpoint. Peripheral to host (IN endpoint): After each write, an internal counter is automatically incremented, by two in 16-bit mode ...
Page 114
NXP Semiconductors Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just before the microcontroller writes the last packet of 62 ...
Page 115
NXP Semiconductors 10.6.6 Endpoint MaxPacketSize register This register determines the maximum packet size for all endpoints, except control 0. The register contains 2 bytes, and the bit allocation is given in Each time the register is written, the Buffer Length ...
Page 116
NXP Semiconductors Table 121. Endpoint Type register (address 0208h) bit allocation Bit 15 Symbol Reset 0 Bus reset 0 Access R/W R/W Bit 7 Symbol reserved Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always ...
Page 117
NXP Semiconductors In counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set to logic 0. The DMA Transfer Counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing ...
Page 118
NXP Semiconductors Table 125. DMA Command register (address 0230h) bit description Bit Table 126. DMA commands Code 00h 01h 02h to 0Dh - 0Eh 0Fh 10h 11h 12h 13h 14h to FFh - 10.7.2 DMA Transfer Counter ...
Page 119
NXP Semiconductors Table 127. DMA Transfer Counter register (address 0234h) bit allocation Bit 31 Symbol Reset 0 Bus reset 0 Access R/W Bit 23 Symbol Reset 0 Bus reset 0 Access R/W Bit 15 Symbol Reset 0 Bus reset 0 ...
Page 120
NXP Semiconductors Bit 7 Symbol DIS_ XFER_CNT Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration Bit 15 to ...
Page 121
NXP Semiconductors Table 132. DMA Hardware register (address 023Ch) bit description Bit 10.7.5 DMA Interrupt Reason register This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a ...
Page 122
NXP Semiconductors Table 134. DMA Interrupt Reason register (address 0250h) bit description Bit Table 135. Internal EOT-functional relation with the DMA_XFER_OK bit INT_EOT 10.7.6 DMA Interrupt Enable register This 2 bytes register ...
Page 123
NXP Semiconductors Table 137. DMA Endpoint register (address 0258h) bit allocation Bit 7 Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 138. DMA Endpoint register (address 0258h) ...
Page 124
NXP Semiconductors Table 140. DMA Burst Counter register (address 0264h) bit description Bit 10.8 General registers 10.8.1 DcInterrupt register The DcInterrupt register consists of 4 bytes. The bit allocation is given in When a ...
Page 125
NXP Semiconductors Bit 7 Symbol VBUS DMA Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit Bit 31 ...
Page 126
NXP Semiconductors Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit Bit 10.8.2 DcChipID register This read-only register contains the chip identification and hardware version numbers. The firmware must check this information to determine functions ...
Page 127
NXP Semiconductors Table 146. DcScratch - Device Controller Scratch register (address 0278h) bit allocation Bit 15 Symbol Reset 0 Bus reset Access R/W R/W Bit 7 Symbol Reset 0 Bus reset Access R/W R/W Table 147. DcScratch - Device Controller ...
Page 128
NXP Semiconductors Table 150. Interrupt Pulse Width register (address 0280h) bit description Bit Symbol Access INTR_PULSE_ R/W WIDTH[15:0] 10.8.7 Test Mode register This 1 byte register allows the firmware to set the DP and DM pins to ...
Page 129
NXP Semiconductors 11. Power consumption Table 153. Power consumption Number of ports working One port working (high-speed ...
Page 130
NXP Semiconductors 12. Limiting values Table 154. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage CC(5V0) V supply voltage CC(C_IN) I latch-up current lu V electrostatic ...
Page 131
NXP Semiconductors 14. Static characteristics Table 156. Static characteristics: digital pins [1] All digital pins , except pins ID, PSW1_N, PSW2_N, PSW3_N and BAT_ON_N +85 C; unless otherwise specified. amb Symbol Parameter V = 1.65 ...
Page 132
NXP Semiconductors Table 158. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Output levels ...
Page 133
NXP Semiconductors Table 161. Static characteristics 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter R pull-up resistance on pin V UP(VBUS) R pull-down resistance on pin ...
Page 134
NXP Semiconductors 15. Dynamic characteristics Table 162. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External ...
Page 135
NXP Semiconductors Table 165. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter t differential rise and fall time FRFM matching Z ...
Page 136
NXP Semiconductors 15.1 Host timing 15.1.1 PIO timing 15.1.1.1 Register or memory write Fig 20. Register or memory write Table 167. Register or memory write +85 C; unless otherwise specified. amb Symbol V = 1.65 ...
Page 137
NXP Semiconductors 15.1.1.2 Register read Fig 21. Register read Table 168. Register read +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t ...
Page 138
NXP Semiconductors Table 169. Register access +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 15.1.1.4 Memory read A[17:1] ...
Page 139
NXP Semiconductors Table 170. Memory read +85 C; unless otherwise specified. amb Symbol t w13 t su13 t su23 15.1.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity ...
Page 140
NXP Semiconductors Table 171. DMA read (single cycle +85 C; unless otherwise specified. amb Symbol t a34 t a44 t h14 15.1.2.2 Single cycle: DMA write Fig 25. DMA write (single cycle) Table 172. DMA ...
Page 141
NXP Semiconductors 15.1.2.3 Multi-cycle: DMA read Fig 26. DMA read (multi-cycle burst) Table 173. DMA read (multi-cycle burst +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t a16 ...
Page 142
NXP Semiconductors 15.1.2.4 Multi-cycle: DMA write Fig 27. DMA write (multi-cycle burst) Table 174. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T ...
Page 143
NXP Semiconductors 15.2 Peripheral timing 15.2.1 PIO timing 15.2.1.1 PIO register read or write CS_N AD[17:1] (read) DATA[31:0] RD_N (write) DATA[31:0] WR_N Fig 28. ISP1761 register access timing: separate address and data buses (8051 style) Table 175. PIO register read ...
Page 144
NXP Semiconductors Table 175. PIO register read or write +85 C; unless otherwise specified. amb Symbol Parameter t d68 3.6 V CC(I/O) Reading t w18 t su18 t h18 t ...
Page 145
NXP Semiconductors 15.2.2 DMA timing 15.2.2.1 DMA read or write (2) DREQ t su19 (1) DACK t su39 RD_N/WR_N (read) DATA [ (write) DATA [ DREQ is continuously asserted until the last transfer is done or ...
Page 146
NXP Semiconductors Table 177. DMA read or write +85 C; unless otherwise specified. amb Symbol Parameter t h19 t w19 t w29 t d29 t h29 t h39 t su29 t su39 t a19 ISP1761_5 ...
Page 147
NXP Semiconductors 16. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT A A ...
Page 148
NXP Semiconductors TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 0.8 mm ball A1 index area ball ...
Page 149
NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction ...
Page 150
NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
Page 151
NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Soldering of through-hole mount packages 18.1 Introduction to soldering through-hole mount ...
Page 152
NXP Semiconductors 18.4 Package related soldering information Table 180. Suitability of through-hole mount IC packages for dipping and wave soldering Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be ...
Page 153
NXP Semiconductors 19. Abbreviations Table 181. Abbreviations Acronym ACK ASIC ATL ATX CS DMA DSC DW EHCI EMI EOP EOT ESD ESR FIFO FS FLS GDMA GPIO GPS HC HNP HS iTD INT ISO ISR ITL LS LSByte MSByte NAK ...
Page 154
NXP Semiconductors Table 181. Abbreviations Acronym PLL PMOS POR PORP PTD RAM RISC SE0 SE1 SIE siTD SOF SRAM SRP SS TT UHCI USB 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for ...
Page 155
NXP Semiconductors 21. Revision history Table 182. Revision history Document ID Release date ISP1761_5 20080313 • Modifications: Changed mini-A, mini-B and mini-AB to micro-A, micro-B and micro-AB, respectively. • Changed On-The-Go Supplement to the USB Specification from Rev. 1.2 to ...
Page 156
NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
Page 157
NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . ...
Page 158
NXP Semiconductors Table 49. DMA Start Address register (address 0344h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 159
NXP Semiconductors Table 103.Interrupt Configuration register (address 0210h) bit description . . . . . . . . . . . . . . . . . . . . . . . .107 Table 104.Debug mode settings . . ...
Page 160
NXP Semiconductors Table 153.Power consumption . . . . . . . . . . . . . . . . . . . .128 Table 154.Limiting values . . . . . . . . . . . . ...
Page 161
NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration ...
Page 162
NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
Page 163
NXP Semiconductors 9.5.1.2 Product ID register (R: 0372h 9.5.2 OTG Control register . . . . . . . . . . . . . . . ...
Page 164
NXP Semiconductors 22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 155 23 Contact information ...