ISP1761BE STEricsson, ISP1761BE Datasheet - Page 101

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
10.1.1.4 Starting DMA
10.1.1.5 DMA stop and interrupt handling
peripheral controller. If DMA is not required by the application, DMACLKON can be
permanently disabled to save current. The burst counter, DMA bus width, and the polarity
of DC_DREQ and DC_DACK must accordingly be set.
The ISP1761 supports only counter mode DMA transfer. To enable counter mode, ensure
that DIS_XFER_CNT in the DcDMAConfiguration register (address: 0238h) is set to zero.
Before starting the DMA transfer, preset the interrupt enable bit IEDMA in the Interrupt
Enable register (address: 0214h) and the DMA Interrupt Enable register (address: 0254h).
The ISP1761 supports two interrupt trigger modes: level and edge. The pulse width, which
in edge mode, is determined by setting the Interrupt Pulse Width register (address:
0280h). The default value is 1Eh, which indicates that the interrupt pulse width is 1 s.
The minimum interrupt pulse width is approximately 30 ns when set to logic 1. Do not
write a zero to this register.
The interrupt polarity must also be correctly set.
Remark: DMA can apply to all endpoints on the chip. It, however, can only take place for
one endpoint at a time. The selected endpoint is assigned by setting the endpoint number
in the DMA Endpoint register (address: 0258h). It will also internally redirect the endpoint
buffer of the selected endpoint to the DMA controller bus. In addition, it requires a
preceding process to program the endpoint type, the endpoint maximum packet size, and
the direction of the endpoint.
When setting the Endpoint Index register (address: 022Ch), the endpoint buffer of the
selected endpoint is directed to the internal CPU bus for the PIO access. Therefore, it is
required to reconfigure the Endpoint Index register with endpoint number, which is not an
endpoint number in use for the DMA transfer to avoid any confusion.
Dynamically assign the DMA Transfer Counter register (address: 0234h) for each DMA
transfer.
The transfer will end once transfer counter reaches zero. Bit DMA_XFER_OK in the DMA
Interrupt Reason register (address: 0250h) will be asserted to indicate that the DMA
transfer has successfully stopped. If the transfer counter is larger than the burst counter,
the DC_DREQ signal will drop at the end of each burst transfer. DC_DREQ will reassert at
the beginning of each burst. For a 32-bit DMA transfer, the minimum burst length is
4 bytes. This means that the burst length is only one DMA cycle. Therefore, DC_DREQ
and DC_DACK will toggle by each DMA cycle. For a 16-bit DMA transfer, the minimum
burst length is 2 bytes.
Setting bit GDMA read or GDMA write in the DMA Command register (address: 0230h)
will start the DMA transfer.
Remark: DACK and CS_N should not be active at the same time.
The DMA transfer will either successfully be completed or terminated, which can be
identified by reading the status in the DcInterrupt register (address: 0218h) and DMA
Interrupt Reason register (address: 0250h).
If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means that the
transfer counter has reached zero and the DMA transfer is successfully stopped.
Rev. 05 — 13 March 2008
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
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