ISP1761BE STEricsson, ISP1761BE Datasheet - Page 112

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 112. Control Function register (address 0228h) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
R/W
7
0
0
Table 113. Control Function register (address 0228h) bit description
Bit
7 to 5 -
4
3
2
1
0
reserved
R/W
Symbol
CLBUF
VENDP
DSEN
STATUS
STALL
6
0
0
[1]
Description
reserved
Clear Buffer: Logic 1 clears the RX buffer of the indexed endpoint; the TX
buffer is not affected. The RX buffer is automatically cleared once the endpoint
is completely read. This bit is set only when it is necessary to forcefully clear
the buffer.
Remark: If using double buffer, to clear both the buffers issue the CLBUF
command two times, that is, set and clear this bit two times.
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint for
sending on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is
set only when it is necessary to validate the endpoint with the FIFO byte count
that is below the Endpoint MaxPacketSize.
Data Stage Enable: This bit controls the response of the ISP1761 to a control
transfer. After the completion of the set-up stage, firmware must determine
whether a data stage is required. For control OUT, firmware will set this bit and
the ISP1761 goes into the data stage. Otherwise, the ISP1761 will NAK the
data stage transfer. For control IN, firmware will set this bit before writing data to
the TX FIFO and validate the endpoint. If no data stage is required, firmware
can immediately set the STATUS bit after the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the
device and the IN token is acknowledged by the PC host. This bit cannot be
read back and reading this bit will return logic 0.
Status Acknowledge: Only applicable for control IN and OUT.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is completed
and a SETUP token is received. No interrupt signal will be generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK
following the OUT token (host-to-peripheral)
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
Remark: Data transfers preceding the status stage must first be fully completed
before the STATUS bit can be set.
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for
isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the
stalled endpoint because the internal logic picks up from where it is stalled.
Therefore, the Data Toggle bit must be reset by disabling and re-enabling the
corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in
the Endpoint Type register) to reset the PID.
R/W
5
0
0
Rev. 05 — 13 March 2008
CLBUF
R/W
4
0
0
VENDP
R/W
3
0
0
DSEN
W
2
0
0
Hi-Speed USB OTG controller
STATUS
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
STALL
111 of 163
R/W
0
0
0