ISP1761BE STEricsson, ISP1761BE Datasheet - Page 114

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 116. Buffer Length register (address 021Ch) bit description
Table 117. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
15 to 0 DATACOUNT
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
Symbol
[15:0]
10.6.5 DcBufferStatus register
R/W
7
0
0
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just
before the microcontroller writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use the VENDP bit in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
This register is accessed using an index. The endpoint index must first be set before
accessing this register for the corresponding endpoint. It reflects the status of the endpoint
FIFO.
Remark: This register is not applicable to the control endpoint.
Remark: For the endpoint IN data transfer, firmware must ensure a 200 ns delay between
writing of the data packet and reading the DcBufferStatus register. For the endpoint OUT
data transfer, firmware must also ensure a 200 ns delay between the reception of the
endpoint interrupt and reading the DcBufferStatus register. For more information, refer to
Ref. 10 “ISP1760/1 Frequently Asked Questions
Table 118. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit
Access Value
R/W
Bit
7 to 2
1 to 0
Table 117
R/W
6
0
0
0000h
Symbol
-
BUF[1:0]
description
shows the bit allocation of the DcBufferStatus register.
Description
Data Count: Determines the current packet size of the indexed endpoint
FIFO.
R/W
5
0
0
reserved
Description
reserved
Buffer:
00 — The buffers are not filled.
01 — One of the buffers is filled.
10 — One of the buffers is filled.
11 — Both the buffers are filled.
Rev. 05 — 13 March 2008
[1]
R/W
4
0
0
R/W
3
0
0
(AN10054)”.
R/W
2
0
0
Hi-Speed USB OTG controller
BUF1
R
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
BUF0
113 of 163
R
0
0
0