ISP1761BE STEricsson, ISP1761BE Datasheet - Page 118

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
10.7.2 DMA Transfer Counter register
Table 125. DMA Command register (address 0230h) bit description
Table 126. DMA commands
This 4 bytes register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in
For IN endpoint — Because there is a FIFO in the ISP1761 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for the data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared for the endpoint buffer, until all the data has
been read from the DMA FIFO.
Bit
7 to 0
Code
00h
01h
02h to 0Dh -
0Eh
0Fh
10h
11h
12h
13h
14h to FFh -
Name
GDMA Read
GDMA Write
Validate Buffer
Clear Buffer
-
Reset DMA
-
GDMA Stop
Symbol
DMA_CMD[7:0]
Rev. 05 — 13 March 2008
Description
Generic DMA IN token transfer: Data is transferred from the
external DMA bus to the internal buffer.
Generic DMA OUT token transfer: Data is transferred from the
internal buffer to the external DMA bus.
reserved
Validate Buffer (for debugging only): Request from the
microcontroller to validate the endpoint buffer, following a
DMA-to-USB data transfer.
Clear Buffer: Request from the microcontroller to clear the endpoint
buffer, after a DMA-to-USB data transfer. Logic 1 clears the TX
buffer of the indexed endpoint; the RX buffer is not affected. The TX
buffer is automatically cleared once data is sent on the USB bus.
This bit is set only when it is necessary to forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the
Clear Buffer command two times, that is, set and clear this bit two
times.
reserved
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, RD_N and WR_N handshake pins
will temporarily be asserted. This can confuse the external DMA
controller. To prevent this, start the external DMA controller only
after the DMA reset.
reserved
GDMA stop: This command stops the GDMA data transfer. Any
data in the OUT endpoint that is not transferred by the DMA will
remain in the buffer. The FIFO data for the IN endpoint will be
written to the endpoint buffer. An interrupt bit will be set to indicate
that the DMA Stop command is complete.
reserved
Description
DMA command code; see
Table
Hi-Speed USB OTG controller
126.
© NXP B.V. 2008. All rights reserved.
ISP1761
Table
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127.