ISP1761BE STEricsson, ISP1761BE Datasheet - Page 125

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
VBUS
R/W
7
0
0
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
DMA
R/W
6
0
0
description
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
-
EP0SETUP
VBUS
DMA
HS_STAT
RESUME
SUSP
HS_STAT
R/W
5
0
0
Rev. 05 — 13 March 2008
Description
reserved
Logic 1 indicates the endpoint 7 TX buffer as interrupt source.
Logic 1 indicates the endpoint 7 RX buffer as interrupt source.
Logic 1 indicates the endpoint 6 TX buffer as interrupt source.
Logic 1 indicates the endpoint 6 RX buffer as interrupt source.
Logic 1 indicates the endpoint 5 TX buffer as interrupt source.
Logic 1 indicates the endpoint 5 RX buffer as interrupt source.
Logic 1 indicates the endpoint 4 TX buffer as interrupt source.
Logic 1 indicates the endpoint 4 RX buffer as interrupt source.
Logic 1 indicates the endpoint 3 TX buffer as interrupt source.
Logic 1 indicates the endpoint 3 RX buffer as interrupt source.
Logic 1 indicates the endpoint 2 TX buffer as interrupt source.
Logic 1 indicates the endpoint 2 RX buffer as interrupt source.
Logic 1 indicates the endpoint 1 TX buffer as interrupt source.
Logic 1 indicates the endpoint 1 RX buffer as interrupt source.
Logic 1 indicates the endpoint 0 data TX buffer as interrupt source.
Logic 1 indicates the endpoint 0 data RX buffer as interrupt source.
reserved
Logic 1 indicates that a SETUP token was received on endpoint 0.
Logic 1 indicates a transition from LOW to HIGH on V
When implementing a pure host or peripheral, the OTG_DISABLE bit in
the OTG Control register (374h) must be set to logic 1 so that the VBUS
bit is updated with the correct value.
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
High-Speed Status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set when the system
goes into the full-speed suspend.
Resume status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
Suspend status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
RESUME
R/W
4
0
0
SUSP
R/W
3
0
0
PSOF
R/W
2
0
0
Hi-Speed USB OTG controller
SOF
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
BUS
.
unchanged
BRESET
124 of 163
R/W
0
0