ISP1761BE STEricsson, ISP1761BE Datasheet - Page 26

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
7.6 Power management
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
The ISP1761 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in a PCI Hi-Speed USB host
controller with a Hi-Speed USB hub attached.
While the ISP1761 is set in suspend mode, main internal clocks will be stopped to ensure
minimum power consumption. An internal LazyClock of 100 kHz
running. This allows initiating a resume on one of these events:
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional.
These pins must be connected to the GPIO pins of a processor.
The awake state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the ISP1761 is in the suspend state.
HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors
because in the ISP1761 suspended state these pins become 3-state and can be pulled
down, driving them externally by switching the processor’s GPIO lines to output mode to
generate the ISP1761 wake-up.
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are 3-state
output and also input to the internal wake-up logic.
When in suspend mode, the ISP1761 internal wake-up circuitry will sense the status of
the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:
The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down
Control register. The default value of this timer is 10 ms, meaning that the resume state
will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD
register is set to logic 1, the host controller will go into a permanent resume; the normal
functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
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External USB device connect or disconnect
CS_N signal asserted when the ISP1761 is accessed
Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the
host controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical level
will wake up the peripheral controller
If the pins remain pulled-up, no wake-up will be generated because a HIGH is sensed
by the internal wake-up circuit.
If the pins are externally pulled LOW, for example, by the GPIO lines or just a test by
jumpers, the input to the wake-up circuitry becomes LOW and the wake-up is
internally initiated.
Rev. 05 — 13 March 2008
Hi-Speed USB OTG controller
40 % will continue
© NXP B.V. 2008. All rights reserved.
ISP1761
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