ISP1761BE STEricsson, ISP1761BE Datasheet - Page 33

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ISP1761BE

Manufacturer Part Number
ISP1761BE
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1761BE

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

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NXP Semiconductors
8. Host controller
ISP1761_5
Product data sheet
Table 8
Table 8.
Address
EHCI capability registers
0000h
0002h
0004h
0008h
EHCI operational registers
0020h
0024h
0028h
002Ch
0060h
0064h
0130h
0134h
0138h
0140h
0144h
0148h
0150h
0154h
0158h
Configuration registers
0300h
0304h
0308h
030Ch
0330h
0334h
0338h
All registers range from 0000h to 03FFh. These registers can be read or written as
double word, that is 32-bit data.
Operational registers range from 0000h to 01FFh. Host controller-specific and OTG
controller-specific registers range from 0300h to 03FFh. Peripheral controller-specific
registers range from 0200h to 02FFh.
17 address lines (15/14 addresses, necessary to address up to 64 kB range on a
16-bit/32-bit data bus configuration + additional 2 addresses for bank select/virtual
segmentation for memory address access time improvement). A0 is not defined
because 8-bit access is not implemented.
shows the bit description of the registers.
Host controller-specific register overview
Register
CAPLENGTH
HCIVERSION
HCSPARAMS
HCCPARAMS
USBCMD
USBSTS
USBINTR
FRINDEX
CONFIGFLAG
PORTSC1
ISO PTD Done Map
ISO PTD Skip Map
ISO PTD Last PTD
INT PTD Done Map
INT PTD Skip Map
INT PTD Last PTD
ATL PTD Done Map
ATL PTD Skip Map
ATL PTD Last PTD
HW Mode Control
HcChipID
HcScratch
SW Reset
HcDMAConfiguration
HcBufferStatus
ATL Done Timeout
Rev. 05 — 13 March 2008
Reset value
20h
0100h
0000 0011h
0000 0086h
0008 0B00h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 2000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0100h
0001 1761h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
Hi-Speed USB OTG controller
References
Section 8.1.1 on page 33
Section 8.1.2 on page 33
Section 8.1.3 on page 33
Section 8.1.4 on page 34
Section 8.2.1 on page 35
Section 8.2.2 on page 36
Section 8.2.3 on page 37
Section 8.2.4 on page 37
Section 8.2.5 on page 38
Section 8.2.6 on page 39
Section 8.2.7 on page 40
Section 8.2.8 on page 41
Section 8.2.9 on page 41
Section 8.2.10 on page 41
Section 8.2.11 on page 41
Section 8.2.12 on page 42
Section 8.2.13 on page 42
Section 8.2.14 on page 42
Section 8.2.15 on page 43
Section 8.3.1 on page 43
Section 8.3.2 on page 45
Section 8.3.3 on page 45
Section 8.3.4 on page 45
Section 8.3.5 on page 46
Section 8.3.6 on page 47
Section 8.3.7 on page 48
© NXP B.V. 2008. All rights reserved.
ISP1761
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