ISP1761BE STEricsson, ISP1761BE Datasheet - Page 47

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
Table 40.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit
allocation
8.3.5 HcDMAConfiguration register
R/W
R/W
R/W
R/W
R/W
R/W
15
31
23
15
0
7
0
0
0
0
7
0
Table 39.
The bit allocation of the HcDMAConfiguration register is given in
Bit
31 to 2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
14
30
22
14
0
6
0
0
0
0
6
0
reserved
SW Reset - Software Reset register (address 030Ch) bit description
Symbol
-
RESET_HC
RESET_ALL
[1]
R/W
R/W
R/W
R/W
R/W
R/W
13
29
21
13
0
5
0
0
0
0
5
0
reserved
Rev. 05 — 13 March 2008
Description
reserved; write logic 0
Reset Host Controller: Reset only host controller-specific registers
(only registers with address below 300h).
0 — No reset
1 — Enable reset
Reset All: Reset all host controller and CPU interface registers.
0 — No reset
1 — Enable reset
DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
DMA_COUNTER[7:0]
[1]
R/W
R/W
R/W
R/W
R/W
R/W
12
28
20
12
0
4
0
0
0
0
4
0
reserved
[1]
R/W
R/W
R/W
R/W
R/W
R/W
BURST_LEN[1:0]
11
27
19
11
0
3
0
0
0
0
3
0
R/W
R/W
R/W
R/W
R/W
R/W
10
26
18
10
0
2
0
0
0
0
2
0
Hi-Speed USB OTG controller
Table
ENABLE
RESET_
_DMA
R/W
R/W
R/W
R/W
R/W
R/W
17
25
9
0
1
0
0
HC
0
9
0
1
0
40.
© NXP B.V. 2008. All rights reserved.
ISP1761
DMA_READ_
WRITE_SEL
RESET_
R/W
R/W
R/W
R/W
16
R/W
R/W
ALL
24
8
0
0
0
0
0
46 of 163
8
0
0
0