ISP1761BE STEricsson, ISP1761BE Datasheet - Page 53

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
Table 52.
Bit
31 to 16
15 to 13
12
11
10
9 to 6
5
4
3
[1]
Power Down Control register (address 0354h) bit description
Symbol
CLK_OFF_
COUNTER
[15:0]
-
PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors.
PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors.
VBATDET_
PWR
-
BIASEN
VREG_ON
OC3_PWR
Rev. 05 — 13 March 2008
Description
Clock Off Counter: Determines the wake-up status duration after any
wake-up event before the ISP1761 goes back into suspend mode.
This time-out is applicable only if, during the given interval, the host
controller is not programmed back to normal functionality.
03E8h — The default value. It determines the default wake-up interval
of 10 ms. A value of zero implies that the host controller never wakes
up on any of the events. This may be useful when using the ISP1761
as a peripheral to save power by permanently programming the host
controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up
time of 500 ms.
The setting of this register is based on the 100 kHz
frequency. It is a multiple of 10 s period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation
to these bits with any value fixes the clock off counter at 1400h. This
value is equivalent to a fixed wake-up time of 50 ms.
reserved
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
0 — Port 2 internal pull-down resistors are not connected.
1 — Port 2 internal pull-down resistors are connected.
V
0 — V
1 — V
reserved; write reset value
Bias Circuits Powered: Controls the power to internal bias circuits.
0 — Internal bias circuits are not powered in suspend.
1 — Internal bias circuits are powered in suspend.
V
regulators when the
0 — Internal regulators are normally powered in suspend.
1 — Internal regulators switch to low power mode (in suspend mode).
OC3_N Powered: Controls the powering of the overcurrent detection
circuitry for port 3.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
BAT
REG
Detector Powered: Controls the power to the V
Powered: Enables or disables the internal 3.3 V and 1.8 V
BAT
BAT
detector is powered or enabled in suspend.
detector is not powered or disabled in suspend.
ISP1761
is in suspend.
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
40 % LazyClock
BAT
detector.
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