ISP1761BE STEricsson, ISP1761BE Datasheet - Page 54

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 53.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation
8.4.1 HcInterrupt register
R/W
R/W
R/W
8.4 Interrupt registers
31
23
15
0
0
0
Table 52.
[1]
The bits of this register indicate the interrupt source, defining the events that determined
the INT generation. Clearing the bits that were set because of the events listed is done by
writing back logic 1 to the respective position. All bits must be reset before enabling new
interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN
in the HW Mode Control register.
register.
Bit
2
1
0
[1]
For a 32-bit operation, the default wake-up counter value is 10 s. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
R/W
R/W
R/W
30
22
14
0
0
0
Power Down Control register (address 0354h) bit description
Symbol
OC2_PWR
OC1_PWR
HC_CLK_
EN
reserved
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 05 — 13 March 2008
[1]
Description
OC2_N Powered: Controls the powering of the overcurrent detection
circuitry for port 2.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
OC1_N Powered: Controls the powering of the overcurrent detection
circuitry for port 1.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
Host Controller Clock Enabled: Controls internal clocks during
suspend.
0 — Clocks are disabled during suspend. This is the default value.
Only the LazyClock of 100 kHz
this bit is logic 0. If clocks are stopped during suspend, CLKREADY
IRQ will be generated when all clocks are running stable.
1 — All clocks are enabled even in suspend.
R/W
R/W
R/W
28
20
12
0
0
0
Table 53
reserved
reserved
[1]
[1]
shows the bit allocation of the HcInterrupt
R/W
R/W
R/W
27
19
11
0
0
0
OTG_IRQ
40 % will be left running in suspend if
R/W
R/W
R/W
26
18
10
0
0
0
Hi-Speed USB OTG controller
ISO_IRQ
R/W
R/W
R/W
25
17
…continued
0
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1761
ATL_IRQ
R/W
R/W
R/W
53 of 163
24
16
0
0
8
0