ISP1761BE STEricsson, ISP1761BE Datasheet - Page 79

no-image

ISP1761BE

Manufacturer Part Number
ISP1761BE
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1761BE

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1761BE
Manufacturer:
ST
0
Part Number:
ISP1761BE
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
ISP1761BE
Quantity:
56
Company:
Part Number:
ISP1761BE
Quantity:
1 000
Part Number:
ISP1761BE-S
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1761BEGE
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1761BEUM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 74.
ISP1761_5
Product data sheet
Bit
DW7
63 to 40
39 to 32
DW6
31 to 24
23 to 16
15 to 8
7 to 0
DW5
63 to 56
55 to 48
47 to 40
39 to 32
DW4
31 to 29
28 to 26
25 to 23
22 to 20
19 to 17
16 to 14
13 to 11
10 to 8
7 to 0
Symbol
reserved
ISO_IN_7[7:0] HW — writes
ISO_IN_6[7:0] HW — writes
ISO_IN_5[7:0] HW — writes
ISO_IN_4[7:0] HW — writes
ISO_IN_3[7:0] HW — writes
ISO_IN_2[7:0] HW — writes
ISO_IN_1[7:0] HW — writes
ISO_IN_0[7:0] HW — writes
Status7[2:0]
Status6[2:0]
Status5[2:0]
Status4[2:0]
Status3[2:0]
Status2[2:0]
Status1[2:0]
Status0[2:0]
Start and complete split for isochronous: bit description
SCS[7:0]
SA[7:0]
Access
-
SW — writes (0
HW — writes (1
After processing
HW — writes
HW — writes
HW — writes
HW — writes
HW — writes
HW — writes
HW — writes
HW — writes
SW — writes (0
HW — writes (1
After processing
1)
1)
0)
0)
Rev. 05 — 13 March 2008
Value Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bytes received during SOF7, if SA[7] is set to 1 and frame
number is correct.
Bytes received during SOF6, if SA[6] is set to 1 and frame
number is correct.
Bytes received during SOF5, if SA[5] is set to 1 and frame
number is correct.
Bytes received during SOF4, if SA[4] is set to 1 and frame
number is correct.
Bytes received during SOF3, if SA[3] is set to 1 and frame
number is correct.
Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1
and frame number is correct.
Bytes received during SOF1, if SA[1] is set to 1 and frame
number is correct.
Bytes received during SOF0 if SA[0] is set to 1 and frame
number is correct.
All bits can be set to one for every transfer. It specifies which
Start split and complete split active bits, SA = 0000 0001 and
CS in Frame2.
Isochronous IN or OUT status of SOF7
Isochronous IN or OUT status of SOF6
Isochronous IN or OUT status of SOF5
Isochronous IN or OUT status of SOF4
Isochronous IN or OUT status of SOF3
Isochronous IN or OUT status of SOF2
Isochronous IN or OUT status of SOF1
Isochronous IN or OUT status of SOF0
Bit 0 — Transaction error (IN and OUT)
Bit 1 — Babble (IN token only)
Bit 2 — Underrun (OUT token only)
Specifies which SOF the start split needs to be placed.
For OUT token: When the frame number of bits DW2[7:3]
matches the frame number of the USB bus, these bits are
checked for one before they are sent for the SOF.
For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be
set to 1. Nothing can be set for SOF4 and above.
SOF the complete split needs to be sent. Valid only for IN.
SCS = 0000 0100, will cause SS to execute in Frame0 and
Hi-Speed USB OTG controller
© NXP B.V. 2008. All rights reserved.
ISP1761
78 of 163

Related parts for ISP1761BE