ISP1761BE STEricsson, ISP1761BE Datasheet - Page 95

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 86.
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reset value depends on the corresponding OTG status. For details, see
OTG Status register (address 0378h) bit allocation
9.5.3.1 OTG Status register
B_SESS_
9.5.3 OTG Interrupt registers
END
15
[1]
R
R
0
7
Table 85.
[1]
This register indicates the current state of the signals that can generate an interrupt. The
bit allocation of the register is given in
Table 87.
Bit
2
1
0
Bit
15 to 9
8
[1]
To use port 1 as a host controller, write 0080 0018h to this register after power-on. To use port 1 as a
peripheral controller, write 0006 0400h to this register after power-on.
14
R
R
0
6
0
Symbol
DM_PULLDOWN DM pull-down:
DP_PULLDOWN
DP_PULLUP
reserved
OTG Control register (address set: 0374h, clear: 0376h) bit description
OTG Status register (address 0378h) bit description
Symbol
-
B_SE0_SRP
13
R
R
0
5
0
Rev. 05 — 13 March 2008
Description
0 — Disable
1 — Enable
DP pull-down:
0 — Disable
1 — Enable
0 — The pull-up resistor is disconnected from the DP line. The data
line pulsing is stopped.
1 — An internal 1.5 k pull-up resistor is present on the DP line.
The data line pulsing is started.
Remark: When port 1 is in peripheral mode or it plays the role of a
peripheral while the OTG functionality is enabled, it depends on the
setting of DP_PULLUP and the V
DP line to HIGH through a pull-up resister. V
When 5 V is present on the V
reserved
Description
reserved for future use
2 ms of SE0 detected in the B-idle state
CONN
RMT_
12
R
R
0
4
0
Table
Table
86.
11
ID
[1]
R
R
0
3
87.
BUS
DP_SRP
10
BUS
R
R
pin, V
0
2
0
Hi-Speed USB OTG controller
sensing signal to connect the
BUS
A_B_SESS
= 1.
BUS
_VLD
[1]
R
R
9
0
1
is an internal signal.
© NXP B.V. 2008. All rights reserved.
ISP1761
VBUS_VLD
…continued
B_SE0_
SRP
94 of 163
[1]
R
R
8
0
0