MC14069UBD ON Semiconductor, MC14069UBD Datasheet

Inverters 3-18V CMOS Hex

MC14069UBD

Manufacturer Part Number
MC14069UBD
Description
Inverters 3-18V CMOS Hex
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC14069UBD

Number Of Circuits
6
Logic Family
MC140
Logic Type
CMOS
High Level Output Current
- 4.2 mA
Low Level Output Current
4.2 mA
Propagation Delay Time
125 ns, 75 ns, 55 ns
Supply Voltage (max)
18 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 125 C
Package / Case
SOIC-14
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 18 V
Lead Free Status / Rohs Status
No RoHS Version Available
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin−for−Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
Pb−Free Packages are Available
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
, V
Input or Output Voltage Range
in
out
(DC or Transient)
I
, I
Input or Output Current
in
out
(DC or Transient) per Pin
P
Power Dissipation, per Package
D
(Note 1)
T
Ambient Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature
L
(8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
v (V
or V
) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
or V
). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 8
)
SS
Value
Unit
−0.5 to +18.0
V
−0.5 to V
+ 0.5
V
DD
± 10
mA
500
mW
−55 to +125
°C
−65 to +150
°C
260
°C
and V
should be constrained
in
out
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
MC14069UBCP
P SUFFIX
AWLYYWWG
CASE 646
1
14
SOIC−14
14069UG
D SUFFIX
AWLYWW
CASE 751A
1
14
14
TSSOP−14
069U
DT SUFFIX
ALYWG
CASE 948G
G
1
14
SOEIAJ−14
MC14069UB
F SUFFIX
ALYWG
CASE 965
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
G
Publication Order Number:
MC14069UB/D

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MC14069UBD Summary of contents

Page 1

MC14069UB Hex Inverter The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the ...

Page 2

... Figure 4. Switching Time Test Circuit and Waveforms ORDERING INFORMATION Device MC14069UBCP MC14069UBCPG MC14069UBD MC14069UBDG MC14069UBDR2 MC14069UBDR2G MC14069UBDTR2 MC14069UBDTR2G MC14069UBFEL MC14069UBFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 5

... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 6

... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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